基于fpga和xinlinx ise的小游戏的vhdl程序，希望对你有所帮助！

Learning Verilog Chinese Version Part 2

Quartus II 7.2最完美的license破解器!(Quartus II 7.2 FULL and perfect License!)

一个用VHDL设计的DDS信号发生器，包括两个pics的仿真结果。

说明：  this file describes the steps in building a fifo buffer module in verilog hdl and programming them on an fpga device

very much verilog code for the beginner

数字秒表的实现，我还写个具体的过程要求等，(there is function of clock,it very useful)

各种常用模块的VHDL描叙实例，PDF格式-various modules used VHDL depicts examples, PDF format

FPGA实现FSK调制，带Modelsim仿真，实际系统测试通过，载波信号，信号频率等可调。(FPGA implementation FSK modulation with Modelsim simulation, the actual system test, the carrier signal, the signal frequency is adjustable.)

使用verilog硬件设计语言在FPGA板子上STOPWATCH 秒表设计。(Using verilog hardware design language STOPWATCH stopwatch design on FPGA board.)

说明：  用于FPGA的I2S接收模块，仅供学习和参考(audio-i2s receive.use fpga.)