VHDL 乘法器 源代码，很好的VHDL 入门学习例程序

使用verilog硬件设计语言在FPGA板子上STOPWATCH 秒表设计。(Using verilog hardware design language STOPWATCH stopwatch design on FPGA board.)

本文件是可以直接使用下载到FPGA里面使用，里面包含时钟分频电路，串并转换和并串转换电路，多通道信号加权的乘加电路等。-The document may download to FPGA chip to complete the clock divider,serial-to-parallel,parallel-to-serial,and multiple-add circuit for multiple channels weight calculation

本源码为Nios II的开发示例,主要演示基于Nios II的uCOS的移植。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of examples, mainly based on the Nios II shows the uCOS transplant. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.

说明：  一款verilog设计的SRAM控制器，可以实现AHB总线控制的功能。(abcdefghijklmnopqrstuvwxyz)

说明：  fpga实现相关滤波算法中的CSK算法，采用仿真的方式验证结果 fpga是xilinx 仿真工具是vivado2018.2 语言是verilog(The CSK algorithm is implemented in FPGA, and the results are verified by simulation FPGA is Xilinx The simulation tool is vivado 2018.2 Language is Verilog)

位同步例程源代码,FPGA应用领域，Verilog-Bit synchronization routines source code, FPGA applications, Verilog

Verilog语言描述，统计图片的像素值直方图(Verilog，Pictures of the pixel value histogram statistics)

本程式為使用Verilog語言寫控制DRAM的控制模塊, 可以簡易的控制DRAM IC, 本程式已經過系統驗證.(program for the use of the Verilog language to write the control of DRAM control module, be easy to control DRAM IC, the program has been systematically verified.)

基于FPGA的视频图像加密系统 DE2_70+TRDB—D5M+VGA(FPGA-based video encryption system DE2_70+TRDB-D5M+VGA)

saber的仿真模型，是一个电源的，经过调试已经成功(The simulation model of the saber, is a power, after commissioning has been successfully)