VHDL 乘法器 源代码，很好的VHDL 入门学习例程序

This is an UART real time clock

使用vhdl语言在altera公司的up3板上产生vga信号，里面有详细的解析和说明，是一个很好的教程。-use of the VHDL language ALTERA company"s board up3 have vga signal containing a detailed analysis and explanation is a good guide.

attachement of attachments..bits pilani

Modelsim+DC开发的4级流水线结构的MIPS CPU(mips 4level cpu)

verilog 简易频率计的设置，包括整个工程(verilog simple frequency meter settings, including the entire project)

（1）距离算法研究和设计； （2）采用FPGA/CPLD实现。 -(1) distance algorithm and design (2) using FPGA/CPLD implementation.

酷睿系列流水灯通用程序，来回往返流水，点亮led(ledwater for ep2c8q208c8)

文档主要是关于TFT-LCD的相关资料，是有关TFT-lcd芯片的结构与设计理念，对于在这方面学习的朋友有比较大帮助(402 output thinfilm transistorliqu idcrystal display(TFT-LCDdriver integrated circui(ICwith power controlbasedon the number of color stobe displaye disdescribed. Toachievethistypeofpowercontrol,referencevoltagebuffersare turnedonandoffaccordingtotheselectednumberofcolors.)

DDS中的正余弦生成，初始相位相差90度，可自行改变输出频率(Cosine generation of DDS, the initial phase difference of 90 degrees, the output frequency can be changed on their own)

FPGA功耗分析工具EPE用于分析FPGA系统的功耗(FPGA power analysis tools EPE is used to analyze the power consumption of the FPGA system)