这里有一个实例

是用于pci开发的核，可以将硬件的信息映射到然间上来 节省出开发人员用于了解硬件的时间 -Pci developed for nuclear, hardware information can be mapped to the inter-ran up to save the developers time to understand the hardware

本模块是实现格雷码和二进制码的转换，并给出仿真测试文件(This module is to achieve the conversion of Gray code and binary code, and give the simulation test file)

VHDL语言教材-The teaching material of VHDL Language

32bit floating point addition

在开发板EGO1上实现的图形记忆游戏，白块按下确认建，黑色块不按确认键(memory game in verilog)

verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.

带自适应波特率发生器UART实现，经过FPGA验证的！-UART baud rate generator with adaptive realization, after FPGA validation!

LFSR模块，单个模块，实现移位寄存器，生成测试用pattern-LFSR

利用verilog驱动LCD1602 本实验是用LCD1602显示英文。（LCD带字库）(//Use verilog driver LCD1602// video tutorial for all of us 21EDA e-learning board// The experiment is LCD1602 display in English. (LCD with font))

以太网协议 TCP/IP/DHCP协议verilog实现(Ethernet IP/TCP/DHCP verilog source code)