这里有一个实例

用verilog编写的包含有与DSP通信，三电平svpwm实现的程序，(Written in verilog contains communicate with the DSP, three-level svpwm realize the procedures)

the basic system of nexys3(soft core)

实现一个循环冗余码,是老师给的例子，别的同学已经验证-a cycle ruduandency code

可在FPGA上运行的8051 IP coore，是学习FPGA及SPOC的好资料。 (8051 IP coore, can be run on the FPGA is good information to learn FPGA and SPOC.)

基于diligent公司的basys2开发板的四位有符号二进制数的除法

verilog实现计时器timer，可直接用于芯片开发中。(verilog achieve timer, it can be directly used for chip development.)

说明：  利用FPGA实现SDH开销中帧头A1A2的检测(FPGA implementation using SDH overhead in the frame header detection of A1A2)

SDRAM 控制器的多 CPU 系统的公断人将调度内存访问。

EDA技术以EDA软件工具为开发环境，以可编程逻辑器件为实验载体，实现源代码编程和仿真功能。VHDL作为一种标准化的硬件描述语言用于描述数字系统的结构、行为、功能和接口。本设计提出了一种基于VHDL语言的编码器和译码器的实现方法。编码器与译码器是计算机电路中基本的器件，本课程设计采用EDA技术设计编码和译码器。编码器由8线-3线优先编码器作为实例代表，译码器则包含3线-8线译码器和2线-4线译码器两个实例模块组成。课程设计采用硬件描述语言VHDL把电路按模块化方式进行设计，然后进行编程、时序仿真和分析等。课程设计结构简单，使用方便，具有一定的应用价值。 (EDA technology take the EDA software as tools for the development of the environment,programmable logic devices in experimental carrier,the realiztion of the source code programming and simulation. The VHDL as a standardized hardware description language used to describe the struction of digital systems,behavior,function and interface. The paper proposes a method for encoder and decoder based on the VHDL language.Encoder and decoder is a basic computer circuit devices.This Curriculum design by EDA design encoder and decoder.Encoders from 8- 3 priority encoder for example,and decoder includes 3- 8 decoder and the 2- 4 examples of the two decoder modules.And then to program, the timing simulation and analysis.Curriculum design, simple structure, easy to use and has a value.)

本文利用FPGA 可以弥补硬件插补器的不足，是执行速度提高，且可与运动控制部分很好的集成，制成运动控制器，实现高速运动控制