Electric Guitar Digital Effects Processor

关于USB开发的verilog开发程序，非常的全面，学习FPGA开发时用得着。(About USB development verilog development process, very comprehensive, learning FPGA development time worthwhile.)

王金明的一些学习VHDL的子-Wang Jinming study of some subset of VHDL

多进制数字频率调制(MFSK)系统VHDL程序-Multi-band digital frequency modulation (MFSK) system VHDL procedures

The project is used to perform the operation of 4 bit arethmatic and logical operation. the projcet is implemented in spartan 3E

程序在报告中，要　用QuartusII运行，注意从word到运行环境中，可能有个别符号不兼容，重新在运行环境中输入那些符号就可以了-procedures in the report, with QuartusII operations, the attention to word from the operating environment, Some individual symbols are not compatible, the operating environment to re-enter those symbols on the

UML2 apprendre a modeliser a l aide de UML

verilog ADPLL file with testbench

七段LED数码管显示译码器设计，将输入的16位二进制数据分别输出到4个数码管上(Seven-segment LED display decoder design, the input of 16 binary data are output to the four digital tube)

基于nios的vga显示实验，自制的ip核。可以按照自己的需求改写ip(Nios to vga display ip nuclear experiments, homemade. Can be rewritten in accordance with their own needs ip)

this come from alter ,you can look and find it on line about jtag.