DE2 115 BCD 3 位数计数器

利用VHDL语言描述出一个双脉冲，可任意设置两脉冲长和中间时间间隔。(A double pulse is described in VHDL language, and the two pulse length and the intermediate time interval can be arbitrarily set.)

SPI读写AD9361，通过串口回读关键寄存器读写是否正确。(SPI reads and writes AD9361, reads and writes the key registers correctly through the serial port.)

基于FPGA实现交织 在通信中交织的算法 已在板上通过测试(based on FPGA to Interleaver)

基于FPGA的DDS。可以产生三种波形：正弦，方波，三角波。频率分辨率0.012Hz。频率从0至25MHz任意可调。(FPGA-based DDS. Can produce three waveforms: sine, square, triangle wave. Frequency resolution 0.012Hz. Frequency is adjustable from 0 to 25MHz.)

曼彻斯特编解码，是Verilog语言代码，不多介绍了，用途非常广泛了-Manchester encoding and decoding is the Verilog language code, introduced a few, a very extensive use

本程序实现两个整数平方和相加并且输出结果-the program two integers and the sum of squared output

modelsim下的60进制计数器源码和测试激励文件(modelsim M counter 60 under the source file and test incentives)

七段LED数码管显示译码器设计，将输入的16位二进制数据分别输出到4个数码管上(Seven-segment LED display decoder design, the input of 16 binary data are output to the four digital tube)

说明：  串口通信通用模块，FPGA Verilog语言 ise，vivado环境(uart,FPGA Verilog, ise,vivado)

获取主机CPU信息，VS2008编译通过，含详细说明(Get information on the host CPU, VS2008 compiler, containing detailed instructions)