这是一个用VHDL语言实现的非常实用的表决器

按键控制led灯亮灭顺序，从左到右跑或者从右往左跑(Press button to control the LED lights on and off)

用Hspice实现一个三输入异或门，并分析其功耗和延时。(A three input XOR gate is implemented by Hspice, and its power consumption and delay are analyzed.)

Verilog HDL编写的CPU模型，很经典，比较通用-Verilog HDL prepared by the CPU model, classic, more generic

SDRAM 控制器的多 CPU 系统的公断人将调度内存访问。

高级加密标准AES的FPGA实现，支持128，256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format

single cycle mips design by verilog.

讲述了dds直接数字频率合成的基本原理，同时用ＶＨＤＬ语言编写dds原代码用于生成正弦波，并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果-described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for simulation and verification MATLAB sine wave output

Vhdl design z80 for altera users

logic lock 的vhdl源码，altera平台适用。-logic lock the VHDL source code, altera platform.

It is the FSM implemented in Xylinx 14.7 on FPGA