登录
首页 » VHDL » 这是一个用VHDL语言实现的非常实用的表决器

这是一个用VHDL语言实现的非常实用的表决器

于 2022-05-23 发布 文件大小:324.29 kB
0 180
下载积分: 2 下载次数: 1

代码说明:

这是一个用VHDL语言实现的非常实用的表决器-This is a VHDL language with the very practical voting machine

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 3M
    说明:  在FPGA实验操作系统实现ASK,FSK,PSK的调制解调,基带信号由M序列发生器产生,经过AD模块在示波器上进行显示,精油DA模块在同一块实验板上进行解调操作,生成信号控制LED灯的亮灭,并与调制输出信号在示波器上同时展示,并进行对比。基带信号为3MHz。(In the FPGA operating system experiment implementation ASK, FSK, PSK modulation and demodulation of the baseband signal generated by the M sequence generator, through the AD module on the oscilloscope display module, oil DA demodulation operation in the same block experiment board, the signal generation control LED lights off, and the modulated output signal displayed on the oscilloscope at the same time, and compared.)
    2018-02-09 20:07:01下载
    积分:1
  • delayline_b
    基于延迟线的数字脉冲宽度调制,用于电力电子设备的触发信号产生(puls wide modulator based on delayline)
    2015-03-10 15:45:01下载
    积分:1
  • codeloc1k
    说明:  实现电子密码锁的各项功能,经过编译和仿真(Electronic code lock of the function, the compiler and simulation)
    2008-11-09 21:24:14下载
    积分:1
  • Noc
    credit base network on chip(network on chip (noc))
    2020-06-19 11:40:02下载
    积分:1
  • my_lift
    电梯控制,包括楼层按键相应,显示上下状态。(Elevator control, including the floors of the corresponding button to show the whole state.)
    2008-04-24 10:15:52下载
    积分:1
  • uart串行口,用Verilog编写的.供大家参考
    uart串行口,用Verilog编写的.供大家参考-uart serial port, using Verilog prepared. For your reference
    2022-07-17 22:14:09下载
    积分:1
  • RISC-V-Reader-Chinese-v2p1
    说明:  RISC-V 芯片设计规范,很有参考价值,开源芯片设计必备参考资料,希望对大家有帮助。(The RISC-V Foundation is chartered to standardize and promote the open RISC-V instruction set architecture)
    2020-07-01 23:00:02下载
    积分:1
  • Timer programming, vhdl language, can be achieved when the system timer 24
    定时器的编程,vhdl语言,可以实现24时制定时器-Timer programming, vhdl language, can be achieved when the system timer 24
    2022-09-01 16:25:02下载
    积分:1
  • uvm_use_pipelined_ahb
    一个简单的uvm搭建的ahb简单实例,包含了各个组件以及编译的运行的脚本(one sample example about ahb,include every component and compile script)
    2020-10-21 12:17:24下载
    积分:1
  • Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.
    Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.
    2022-07-06 17:29:44下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载