这是一个用VHDL语言实现的非常实用的表决器

说明：  在FPGA实验操作系统实现ASK,FSK,PSK的调制解调，基带信号由M序列发生器产生，经过AD模块在示波器上进行显示，精油DA模块在同一块实验板上进行解调操作，生成信号控制LED灯的亮灭，并与调制输出信号在示波器上同时展示，并进行对比。基带信号为3MHz。(In the FPGA operating system experiment implementation ASK, FSK, PSK modulation and demodulation of the baseband signal generated by the M sequence generator, through the AD module on the oscilloscope display module, oil DA demodulation operation in the same block experiment board, the signal generation control LED lights off, and the modulated output signal displayed on the oscilloscope at the same time, and compared.)

基于延迟线的数字脉冲宽度调制，用于电力电子设备的触发信号产生(puls wide modulator based on delayline)

说明：  实现电子密码锁的各项功能,经过编译和仿真(Electronic code lock of the function, the compiler and simulation)

credit base network on chip(network on chip (noc))

电梯控制，包括楼层按键相应，显示上下状态。(Elevator control, including the floors of the corresponding button to show the whole state.)

uart串行口,用Verilog编写的.供大家参考-uart serial port, using Verilog prepared. For your reference

说明：  RISC-V 芯片设计规范,很有参考价值，开源芯片设计必备参考资料，希望对大家有帮助。(The RISC-V Foundation is chartered to standardize and promote the open RISC-V instruction set architecture)

定时器的编程，vhdl语言，可以实现24时制定时器-Timer programming, vhdl language, can be achieved when the system timer 24

一个简单的uvm搭建的ahb简单实例,包含了各个组件以及编译的运行的脚本(one sample example about ahb，include every component and compile script)

Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.