logic lock 的vhdl源码，altera平台适用。

说明：  TI公司的DAC5578驱动程序，经测试过的，CSDN资源分享(DAC5578 Driver of TI Company Tested and CSDN Resource Sharing)

fpga clock 设计，资料较好，供大家参考，非商用目的哦-fpga clock design, the information is better, for your reference, non-commercial purposes Oh

说明：  FPGA应用状态机版，适合初学者学习状态机三段式，ASMD图的理解和翻译，以及Verilog语言的应用 最后对仿真的一些理解 其中包含HDL设计及testbench描述 根据要求设计了一个能求出一个32bit字中两个相邻0之间最大间隙的电路。(FPGA application state machine version, suitable for beginners to learn state machine three-stage, ASMD chart understanding and translation, and Verilog language application. Finally, some understanding of simulation, including HDL design and testbench description According to the requirements, a circuit is designed to find the maximum gap between two adjacent zeros in a 32 bit word.)

基于verilog的LU分解,本文件包括详细的程序代码，运行文件，以及详细的文档(LU decompose based on verilog)

HDB3编码通过verilog实现，通过modelsim仿真(HDB3 coding is implemented by Verilog and simulated by Modelsim)

code for kcpcm3 : Describes the working of KCPCM3 embedded in picoblaze xilinx-code for kcpcm3 : Describes the working of KCPCM3 embedded in picoblaze xilinx

9针的rs232与fpga之间的串口通信源程序(Rs232 9 pin serial communication with the source between fpga)

UART模块的VHDL语言设计(Design of VHDL language based on UART module)

FPGA UART 发送端程序 verilog语言编写 9600波特率 实用(UART transmit side program verilog language 9600 baud)

sobel边缘检测，用于图像处理。实现了该算法在FPGA上的实现代码。(Sobel edge detection for image processing.Implementation of the algorithm to achieve the FPGA code.)