SDRAM 控制器与仲裁者

32位/33M 从模式(target)PCI接口参考设计，Lattice提供。由于PCI时序较复杂，此设计仅能供参考-32/route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only

c语言编写51单片机键盘扫描程序，方便移植到其他的硬件上去-51 Singlechip c language keyboard scanning procedures for transplantation to other hardware up

Xilinx 公司Spartan-6系列FPGA实现LVDS，带Modelsim仿真文件，已综合。(Xilinx Spartan-6 Series FPGA implements LVDS with Modelsim simulation file, which has been synthesized.)

controller for sending serial data at different speeds

control stepper motor by fpga card with vhdl program

说明：  通过按键输入学号，并循环显示： 电路功能描述：通过Ego1上的按键输入自己的学号（8位10进制数），并存储在32位的寄存器中；8位10进制数输入完成后，实现滚动显示效果。(Enter the student number by pressing the key, and display it in a cycle: Circuit function description: input one's own student number (8-digit decimal number) through the key on ego1, and store it in 32-bit register; after the completion of 8-digit decimal number input, the scrolling display effect is realized.)

ise13.2环境下VHDL编写的半加器器+仿真波形(ise13.2 environment half adder in VHDL simulation waveform control+)

这是本人设计的一个关于VME总线接口的FGPA程序，FPGA一边连接ARM LPC2294，一边连接VME总线，FPGA采用的XILINX公司的SPARTANII系列，程序包包含完整的工程文件-This is my design of a VME bus interface on the FGPA procedures, FPGA side of the connection ARM LPC2294, while connecting VME bus, FPGA using the XILINX Inc. SPARTANII series, the package contains a complete project file

说明：  Verilog简易教程，或者说是讲义，清晰易懂，适合初学者入门使用(Layman' s Guide to Verilog, or a lecture, legible entry to use for beginners)

verilog coding for butterworth filter with cut off frequency with 500hz