described dds direct digital frequency synthesis of the basic tenets addition to...

verilog语法说明，包含verilog golden reference guide，verilog 2001语法(verilog golden reference guide)

使用FPGA实现UART收发。支持多种波特率。(Using FPGA to achieve UART transceiver.)

此源码为线性相位滤波的vhdl源码与设计心的体会，理论分分析与工程实践总结相结合，有非常大的参考价值 可直接使用。 (The source for the linear phase filter VHDL source code and design of the heart experience, theoretical analysis to summarize the combination of engineering practice, a very large reference value can be used directly.)

SDIO slave verilog code

用FPGA实现的VGA接口程序，采用的语言是VHDL硬件描述语言，大家可以参照下看看采用的器件是Altera EP2c35-Using FPGA to achieve the VGA interface program, the language used is VHDL hardware description language, we can see under the light of the devices used are Altera EP2c35

自己用verilog编写的crc16-ccitt码的产生，是并行的。(Crc16-ccitt code written in verilog generate parallel.)

该程序用vhdl编写的vga显示的小游戏，到时屏幕上会显示一个小球，一根棒子，一面墙，棒子可以通过按键控制来移动。而小球在不停的运动，遇到墙会反弹。(Game written by the program with VHDL VGA display, the screen will display a small ball, a stick, a wall, stick to move through the key control. Ball in constant motion, encountered the wall will bounce.)

一种合并频率的方法对时频分析及其有用所以才上传(a fast combination)

说明：  ds18b20的Verilog程序，经测试验证可以使用。注意此版本为DALLS DS18B20而不是DS1820,注意加5K上拉电阻。(ds18b20 the Verilog process can be used to verify by testing. Note that this version rather than DALLS DS18B20 for DS1820, the attention of Canadian 5K pull-up resistor.)

dos下的svga图形库，包括读bmp位图，打点划线等(svga graphics library under dos)