described dds direct digital frequency synthesis of the basic tenets addition to...

timblogiw.c timberdale FPGA LogiWin Video In driver.

交通灯通过数码管显示，几种模式可调，还可以时间可设，适合初学者入门参考学习。(LED traffic lights can be set to several modes adjustable time beginners reference ~ ~ ~)

I2C的实现，可以扩展进而控制有关I2C的器件达到操作员的控制目的。(I2C implementations, can be extended further having control of the I2C device operator control purposes.)

Use serial programming examples matlab GUI implementation, Independent component analysis for image processing, Realize image watermarking, de-noising, plus noise and other functions.

Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.

关于逻辑信号的转变等等的一个程序。还包括显示(Analog-Digital-Wandler)

fault minimization using genetic algorithm

VC++6.0软件生成Altera公司FPGA内部存储器ROM初始化数据mif格式文件。方便通过QuartusII导入波形等参数。强调这个是例子，生成的是一个定点的正弦数据表文件，需要用到的请自行修改源代码。(This software generates internal memory ROM initialization mif format data file for FPGA product by Altera. Facilitate the passage of the waveform parameters such as import QuartusII)

说明：  altera fpga 实现fft，用fft IP核，有matlab仿真代码(Altera FPGA implementation of FFT, FFT IP core, matlab simulation code)

SEG7数码管显示示例程序，适用于ALTERA的CPLD(SEG7 digital display sample program of ALTERA CPLD)