described dds direct digital frequency synthesis of the basic tenets addition to...

带LDN的的同步的预置数端子，并且带CLR的异步清零端-LDN synchronization with the preset number of terminals, and cleared with CLR Asynchronous client

利用LMP的20bit counter,比自带的cout进位要快的多。已经同错综合和时序仿真。-LMP

本书是一本关于VERILOG方面的专业书籍，是通往FPGA设计的基础书籍，值得一看。(thsi is a book of VerilogHDL,also a basic book to master.)

出租车自动计费系统的verilog程序代码(Taxi automated billing system verilog code)

《FPGA数字信号处理与工程应用实践附光盘》配套源代码(FPGA DSP and their applications with verilog HDL)

Matlab to hdl code for Least_square testbench

说明：  用于实现FPGA硬件开发使用的加法器，需要注意的是用Verilog语言实现的(The adder used to realize FPGA hardware development needs to be realized in Verilog language)

一个用于数字解调的应用程序，主要用于数字接收机的应用方面-A demodulator for digital applications, mainly for the application of digital receiver

数字示波器实验，利用AD、DA和VGA三个外设来实现简易示波器，DA外设发送正弦波给AD外设，AD外设解析成数字信号将数据送给VGA外设进行显示。在VGA上可以看到DA外设发送的波形、波形频率和波形峰峰值。(In the experiment of digital oscilloscope, AD, DA and VGA are used to realize simple oscilloscope. DA peripheral transmits sine wave to AD peripheral. AD peripheral resolves into digital signal and sends data to VGA peripheral for display. The waveform, waveform frequency and peak value of DA peripheral can be seen on VGA.)

11 阶FIR 数字滤波器,verolog描述，通过modelsim 6.0 仿真，Quartue综合-11-order FIR digital filter, verolog description, modelsim 6.0 through simulation, Quartue integrated