VHDL的重要PPT资料,对初学者非常有益处

异步FIFO 设计源代码，内涵完整的verilog源代码和测试代码。-Source code for asyn_fifo using verilog language.

this is a sum for 2 digit numbers

evga-indtube.h - Keytable for evga_indtube Remote Controller.

可以给VHDL初学者看的实例，全部经过验证(VHDL beginners can see examples of all the proven)

Verilog-HDL程序设计实用教程收集，内容丰富，设计技巧多样。-Verilog-HDL Design Tutorial practical collection, rich in content and variety of design skills.

文章详细讲述了sdr_sdram控制器的使用和编程思想(sdr_sdram)

使用verilog hdl语言编程正弦波信号，能仿真出结果(Can use verilog HDL language programming sine wave signal, the simulation results )

基于FPGA实现交织 在通信中交织的算法 已在板上通过测试(based on FPGA to Interleaver)

说明：  用Verilog编写的简单的运算单元（ALU），可实现加、减、与、或、异或、非、左、右移等功能(Verilog prepared with simple arithmetic unit (ALU), can be add, subtract, and, or, exclusive-OR, non-, left, and other functions shifted to right)

使用FPGA完成AGC 自动增益的代码，适合初学者(FPGA to complete the use of AGC automatic gain code, suitable for beginners)