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my_uart
一个简单的UART串口程序,能实现数据的发送与接收,但没有奇偶校验等验证数据传输是否正确。(A simple UART serial program, can send and receive data, but there is no parity and other validation data is correct.)
- 2011-08-17 20:48:11下载
- 积分:1
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DDS
Verilog实现DDS线性调频,Verilog实现DDS线性调频(Verilog implementation of DDS linear FM,Verilog implementation of DDS linear FM)
- 2015-07-29 19:59:36下载
- 积分:1
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cyclone and cyclone2 system used in the use 5v, making FPGA chip compatible with...
cyclone和cyclone2用在5v系统里使用方法,使得FPGA芯片在5V系统中兼容-cyclone and cyclone2 system used in the use 5v, making FPGA chip compatible with the 5V system
- 2022-02-03 17:24:31下载
- 积分:1
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8 位修改 Booth 型乘法器
这是基数 4 修改 Booth 型乘法器为 8 位。它可以用于任何大小的操作数的乘法......
- 2022-01-24 13:25:05下载
- 积分:1
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turbo_encode
turbo码的编码程序,verilog HDL,在ISE环境中(turbo code encoding process)
- 2014-03-29 15:09:58下载
- 积分:1
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是verilog例子。初级适用。包括了简单的例子。
是verilog例子。初级适用。包括了简单的例子。-example. The initial application. Including a simple example.
- 2022-05-31 23:36:48下载
- 积分:1
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介绍列昂2微处理器
Inroduce the LEON 2 microprocessor
- 2022-09-20 12:25:02下载
- 积分:1
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Synopsys-RTLSystemC
synopsys的systemc和RTl书籍清晰电子版,专业权威的EDA公司的培训资料(synopsys of systemc and RTl clear electronic version of books, professional authority of the EDA company' s training materials)
- 2010-08-11 11:49:49下载
- 积分:1
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这时一个数字钟的VHDL程序,有计时、校时、整点报时功能,很适合做EDA设计之用...
这时一个数字钟的VHDL程序,有计时、校时、整点报时功能,很适合做EDA设计之用-When a digital clock in VHDL procedures, time, school hours, the whole point timekeeping function, it is suitable for use in EDA Design
- 2022-05-22 23:36:04下载
- 积分:1
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these files are written in verilog but i am uploading in text format
these files are written in verilog but i am uploading in text format
- 2022-02-06 16:09:07下载
- 积分:1