是verilog例子。初级适用。包括了简单的例子。

在altera的FPGA平台上实现rs232串口的自收发通信，速率为115200波特率，PC机使用串口调试助手即可观察结果。包含全部代码与工程，本人亲自测试通过。(Realization of self transmitting and receiving communication serial port of RS232 In altera on the FPGA platform, at a rate of 115200 baud rate, PC using serial debugging assistant can be observed. Contains all the code and engineering, I personally tested by. )

emmc控制芯片CMD命令线主机接口模块,(emmc control chip CMD command line host interface module)

利用VHDL语言编写的一个16分频器，另外可以在程序中修改为任意2N的分频器-use VHDL prepared a 16 dividers, Also in the revision process to be arbitrary 2 N Divider

FPGA设计的I2C总线控制器的MASTER端的程序-FPGA Design of I2C Bus Controller MASTER-side procedures

图像采集、存储控制verilog源代码，fpga控制SAA1117,采集数据存储到sram，仿真编译测试都能通过(Image acquisition, storage, control verilog source code, fpga control SAA1117, collecting data to sram, simulation tests can be compiled by)

自动白平衡的verilog实现 通过逻辑实现了白平衡算法(awb design awb design awb design awb design awb design )

VHDL之二進制轉BCD碼之程式碼，算完整的(Of binary to BCD code VHDL code, operator complete)

完整的跑表设计，时，分，秒都显示，希望能对大家有用，谢啦(Complete stopwatch design, hours, minutes, seconds, show, hoping to be useful for everyone,)

说明：  AES TSAPI Retrieve Event in Non-blocking Mode

在FPGA上实现CAN总线SPI接口通信，使用Verilog语言(Realize SPI interface communication of CAN bus on FPGA, using Verilog language)