介绍列昂2微处理器

Verilog HDL编写的CPU模型，很经典，比较通用-Verilog HDL prepared by the CPU model, classic, more generic

这个是一个基于FPGA的数字图像的整数DCT变换程序，程序高性能地实现了2维DCT变换。-This is an FPGA-based digital image of the integer DCT transform process and procedures to achieve high-performance 2-D DCT transform.

一种基于格雷码的异步FIFO设计与实现,8*8位的fifo VHDL 源码-Gray-code based on the Asynchronous FIFO Design and Implementation

数字钟，简单的数电应用，电子表源程序，常用也使用-watch

基于FPGA的多波形发生器 基于FPGA的多波形发生器-FPGA-based multi-waveform generator based on multi-FPGA Waveform Generator

基于MAX2运用Quartus实现串口通信-MAX2-based use of Quartus Serial Communication

用VERILOG实现自动售货机功能，运行正确，希望有帮助(Use VERILOG implementation vending machine function, correct operation, hope to have help)

rs422标准通讯模块 异步收发 verilog语言编写(rs422 standard communication module asynchronous receiver verilog language)

实现了简单的电子表功能，是24小时，用VHDL所编写的，quartus ii 7.2-To achieve a simple spreadsheet functions, is 24 hours, using VHDL prepared, quartus ii 7.2

CH4CH2CH1VHDL 数字电路参考书所有程序5-CH4CH2CH1VHDL digital circuit reference all proceedings 5