介绍列昂2微处理器

uart 发送模块接收模块及tb，其中可以选择不同波特率进行收发，代码带有详细注释。(UART sending module and receiving module)

基于Verilog的FPGA设计时序分析约束详细解释与使用方法(FPGA timing constraints)

matlab dsp building fpga(matlab dsp building )

时钟分频代码，PWM产生 RTL 源代码。(clock divider，PWM generator RTL Source Code)

说明：  isa MEMORY PLAN eu biu asm

VHDL 语言实现 38译码器 文件中包括 程序 源代码 还有 testbench 测试程序(38 decoder VHDL language implementation, including program source code file, there are testbench test procedures)

This is an UART real time clock

说明：  spi通用串行总线，4线控制，可读写操作(SPI universal serial bus, 4-wire control, readable and writable operation)

synopsys的systemc和RTl书籍清晰电子版，专业权威的EDA公司的培训资料(synopsys of systemc and RTl clear electronic version of books, professional authority of the EDA company' s training materials)

用Vivado IPI搭建的Zynq-7000 PS到PL通信过程，使用了AXI-HP接口，利用AXI-DMA IP实现直接读写DDR的过程，软件可以配置传输尺寸。(The Zynq-7000 PS to PL communication process is built by Vivado IPI. AXI-HP interface is used, and AXI-DMA IP is used to read and write DDR directly. The software can configure the transmission size.)