8 位修改 Booth 型乘法器

VHDL实现 DDS。大家共享吧，一起学习，一起进步(VHDL realize DDS. U.S. to share it with learning, with progress)

基于FPGA的Verilog语言的智能小车，已经经过测试。(FPGA-based smart car Verilog language, and has been tested.)

max plus的入门与应用，适合初学者对max plus ii有一个感性的认识(max plus entry and applications, suitable for beginners to the max plus ii have a perceptual awareness of)

用VERILOG实现自动售货机功能，运行正确，希望有帮助(Use VERILOG implementation vending machine function, correct operation, hope to have help)

可以直接下载到芯片用的带有FIFO的完全UART程序，vhdl语言编写。-Can be directly downloaded to the chip used in the complete UART with FIFO procedures, vhdl language.

vhdl cpu芯片逻辑设计的一部分实现 只有一小部分 大家可以看一下 寄存器 加法器之类的(vhdl cpu chip logic design part of its implementation only a little part everry look and see b=about registers adder and so on)

四选一选择器,输入四个,输出1个.当NM=00时选A 当NM=01时选B 当NM=10时选C 当NM=11时选D-four elected a selector, the importation of four, Output 1. When NM = 00 A at the election when NM = 01 am when the election NM B = C 10:00 when the election NM = 11:00 election D

全部通过，是我的精心设计，完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.

train controler by verilog

simple code of some kind of base decoder based on verilog