FPGA实现数字跑表

关于语音通信信道调制的程序代码，是论文的仿真程序(About voice communication channel modulation code, the authors of the paper simulation program)

it is a fir filter program VerilogHDL.(it is a filter program VerilogHDL fir.)

本实验实现了一个小的乒乓游戏，VGA显示,代码下载的FPGA板子上验证通过，效果很好。(The experimental realization of a small ping-pong game, VGA display, download the code verified by the FPGA board, with good results.)

verilog实现基于i2s协议接口，在fpga上验证通过。(Verilog implements the interface based on I2S protocol and verifies it on fpga.)

vhdl N-0.5分频方法设计，可以输入任意数值N，即分得到N－0.5的频率。-vhdl N- 0.5-frequency method, we can input arbitrary numerical N, namely, to be N- 0.5 frequencies.

一个简单的总线bus代码，初学者可以借鉴学习-A simple bus-bus code, beginners can learn to learn

turbo码的编码程序,verilog HDL,在ISE环境中(turbo code encoding process)

用verilog语言编写，一个8-bit ALU，可以完成按字节的+、-和与、或、非操作(Using Verilog language, an 8-bit ALU, to be completed by byte+,- And, or, non-operating)

驱动0.96寸的oled显示数字和字母，(Drive 0.96 inch OLED to display numbers and letters.)

source vhdl code of D flipflop logic