FPGA实现数字跑表

fpga永磁同步电机矢量控制系统，包括死区等模块(fpga foc)

files describe how to configure an ADV7180

nios大神进阶，一本非常好的FPGA书籍，从RTL到eclips(nios tech.a very good book learning FPGA tech.)

fpga核心源码，有利于学习，适合初学者学习-fpga core source code, there is conducive to learning, suitable for beginners to learn

Verilog-HDL程序设计实用教程收集，内容丰富，设计技巧多样。-Verilog-HDL Design Tutorial practical collection, rich in content and variety of design skills.

说明：  FPGA按键延时模块，产生key_value和key_flag 可直接例化调用(The key delay module of FPGA)

这是用 vhdl 语言编码的可重构的 fir 滤波器设计 fir 滤波器的实现代码

Routine for I2C in VHDL

说明：  数字逻辑实验课第十二次作业，基于Verilog的Clock时钟(Clock based on Verilog)

完成一个FIR数字滤波器的设计。要求： 1、 基于直接型和分布式两种算法。 2、 输入数据宽度为8位，输出数据宽度为16位。 3、 滤波器的阶数为16阶，抽头系数分别为h[0]=h[15]=0000，h[1]=h[14]=0065，h[2]=h[13]=018F，h[3]=h[12]=035A，h[4]=h[11]=0579，h[5]=h[10]=078E，h[6]=h[9]=0935，h[7]=h[8]=0A1F。 -Completion of a FIR digital filter design. Requirements: one, based on the direct type and distributed two algorithms. 2, input data width of 8, the output data width of 16. 3, filter order of 16 bands, tap coefficients for h [0] = h [15] = 0000, h [1] = h [14] = 0065, h [2] = h [13] = 018F , h [3] = h [12] = 035A, h [4] = h [11] = 0579, h [5] = h [10] = 078E, h [6] = h [9] = 0935, h [7] = h [8] = 0A1F.