FPGA实现数字跑表

fpga控制led灯的闪烁，内容简单，希望对初学者有用.(fpga control led lights flashing, the content is simple, I hope useful. . .)

DDR（双速率）SDRAM控制器参考设计，xilinx提供-DDR (double data rate) SDRAM controller reference design for Xilinx

基于fpga和xinlinx ise的音乐播放器vhdl程序，希望对你有所帮助！-and xinlinx ideally music player VHDL process, and I hope to help you!

基于Verilog HDL出租车计费系统的研制(Based on Verilog HDL Taxi Accounting System)

基于OV7670采集，SDRAM缓存，sobel处理，VGA显示的工程，内有全部代码，基于QUARTUS开发板实现。 FPGA 边缘检测(Based on OV7670 acquisition, SDRAM cache, sobel processing, VGA display project, with all the code, based on QUARTUS development board. FPGA edge detection)

CPLD imlementation of I2C BUS Controller. The description has been made by VHDL

描述了使用FPGA接口PDIUSBD12开发USB接口的流程.-Describes the use of FPGA Interface USB interface PDIUSBD12 development flow.

一种压缩感知信号恢复算法，针对贪婪迭代类算法中的正交匹配追踪（OMP)算法的改进。OMP在每次迭代过程中选择出的原子并不是最优的，无法使本轮迭代中残差的减少最大化。本例程实现了改进的最优OMP算法，即Optimised_OMP，保证每次迭代选出的原子与已选出的原子序列所构成的平面正交，因而可以使残差下降的更快，从而加速算法收敛。(A compressed sensing signal recovery algorithms track (OMP) algorithm and orthogonal matching algorithm greedy iterative class. The OMP selected atoms in each iteration of the process is not optimal, not be able to maximize the reduction of the residual in the current round of iteration. The routines to achieve the optimal OMP algorithm improvements that Optimised_OMP, to ensure that each iteration selected atoms with atomic sequence elected a plane orthogonal, and thus can make the residuals have declined even faster, thus speeding up the algorithm convergence.)

The VHDL Cookbook First Edition July, 1990 Peter J. Ashenden Dept. Computer Science University of Adelaide South Australia

用verilog语言编写的4位算术逻辑单元ALU,功能参考74181，包含.v文件以及测试用.vwf文件-Verilog languages with four arithmetic logic unit ALU, functional reference to 74,181, including. V documents and testing. Vwf document