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一个8位CISC结构的精简CPU,2还提供了编译器
一个8位CISC结构的精简CPU,2还提供了编译器-an eight streamline the structure of the CISC CPU, the two also provided compiler
- 2022-02-28 11:37:41下载
- 积分:1
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8位十六进制频率计设计 根据频率的定义和频率测量的基本原理,测定信号的频率必须有一个脉宽为1s的输入信号脉冲计数允许信号;1s计数结束后,计数值被锁入锁存器,计...
8位十六进制频率计设计 根据频率的定义和频率测量的基本原理,测定信号的频率必须有一个脉宽为1s的输入信号脉冲计数允许信号;1s计数结束后,计数值被锁入锁存器,计数器清零,为下一测频计数周期做好准备。测频控制信号可由一个独立的发生器(FTCTRL)来产生。-8-bit hexadecimal Cymometer designed in accordance with the definition of frequency and frequency of the basic principles of measurement to determine the frequency of the signal must have a pulse width of the input signal for 1s permit pulse counting signal 1s counting after the total value was locked into the lock depositors, counters cleared for the next count cycle frequency measurement ready. Frequency control signal generator may be an independent (FTCTRL) to generate.
- 2022-06-19 17:20:21下载
- 积分:1
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8051的Verilog
8051的Verilog-Verilog OF 8051
- 2022-06-15 04:13:18下载
- 积分:1
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dac5687_interface
说明: verilog语言编写的dac5687的接口程序,串行模式控制。(written dac5687 verilog interface program, serial mode control.)
- 2021-04-23 09:38:48下载
- 积分:1
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5_ADC_Lab
altear max10 adc demo,实验使用了2个adc,最大支持18路adc(altear max 10 demo with 2 adc, max support 18 channel adc)
- 2021-04-21 14:48:49下载
- 积分:1
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RS编码在FPGA上实现的理论和方法,对设计RS编码很有帮助,且FOGA资源占有少...
RS编码在FPGA上实现的理论和方法,对设计RS编码很有帮助,且FOGA资源占有少-RS coding in the FPGA to achieve the theory and method useful for design RS encoding, and possession of less FOGA resources
- 2022-05-07 12:16:18下载
- 积分:1
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C51tou-wen-jian
是51单片机常用头文件定义,直接调用就可以,包括:1602液晶,12864液晶,5110屏,I2C,UART,精确延时函数,PWM调速,DS1302,DS18B20,,,,,,,(51 microcontroller used header file defines direct call can include: 1602 LCD, 12864 LCD, 5110 screen, I2C, UART, precision delay function PWM speed control, DS1302, DS18B20,,,,,)
- 2013-04-15 17:34:22下载
- 积分:1
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mul_ser12
本源码是用Verilog编写的12位移位相加乘法器的设计源码,开发软件为MAX+PLUS,已经测试通过。(The Verilog source code is written in the sum of 12-bit shift multiplier design source code, developing software for the MAX+ PLUS, has been tested.)
- 2011-05-31 14:19:30下载
- 积分:1
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数字钟的VHDL源程序,可以实现在学校、年级的壮举…
数字钟的VHDL源程序,可以实现校时,校分等功能,并在试验箱上运行成功-The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on
- 2022-06-12 19:46:36下载
- 积分:1
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jianpan
说明: 一个简单的键盘接口模块程序,对键盘输入的数据和时钟信号进行过滤。过滤后的数据信号PS2Df将被送入两个11位移位寄存器中(A simple keyboard interface module program filters keyboard input data and clock signals. The filtered data signal PS2Df will be fed into two 11-bit displacement registers.)
- 2020-06-24 02:00:02下载
- 积分:1