JOP kernel source code cache, not easy to find, we must kits

非常好的SDRAM Controller 设计文档。工程必备-SDRAM Controller Design of a very good document. Works required

出租车自动计费系统的verilog程序代码(Taxi automated billing system verilog code)

Frequency meter Verilog implementation for Xilinx XC2C256. MT10T7 7-seg LCD used for output.

说明：  altera fpga 实现fft，用fft IP核，有matlab仿真代码(Altera FPGA implementation of FFT, FFT IP core, matlab simulation code)

标准SDR SDRAM控制器参考设计，Lattice提供的verilog源代码-standard SDR SDRAM controller reference design, the Lattice Verilog source code

8位十六进制频率计设计 根据频率的定义和频率测量的基本原理，测定信号的频率必须有一个脉宽为1s的输入信号脉冲计数允许信号；1s计数结束后，计数值被锁入锁存器，计数器清零，为下一测频计数周期做好准备。测频控制信号可由一个独立的发生器（FTCTRL）来产生。-8-bit hexadecimal Cymometer designed in accordance with the definition of frequency and frequency of the basic principles of measurement to determine the frequency of the signal must have a pulse width of the input signal for 1s permit pulse counting signal 1s counting after the total value was locked into the lock depositors, counters cleared for the next count cycle frequency measurement ready. Frequency control signal generator may be an independent (FTCTRL) to generate.

A 4 bit twisted ring counter is a sequential circuit which produces the following sequence of output values: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001 and then repeats. Design a circuit for a 4 bit twisted ring counter that uses four D flip flops. Draw a state transition diagram, a state table and a schematic for your circuit. Design an alternate implementation using just three flip flops and draw a state transition diagram, state table and a schematic for your circuit. If your designs are extended to implement an n bit twisted ring counter, how many flip flops are required using each of the two approaches. In what situations would you prefer the first method? In what situations would you prefer the second?

本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.

Altera大学计划程序包，基于Nios II的源代码(Altera University program package, based on the Nios II source code)

本例是一个6层电梯的控制系统,VHDL原程序,状态机,控制器-This case is a 6-storey elevator control system, VHDL original procedures, state machine, controller