最近组长给分配的任务，这几天一直在做，比较郁闷的是用的器件是XC400XL系列的，只有ISE4.1支持，用惯了7.1i的我还是要适应一阵子（关键4.1是一个试用...

浙江大学体系结构实验课代码，5级流水线实现旁路和停顿(5-stage pipeline to achieve realization of the bypass pipeline bypass pause 5 pause)

说明：  简单的单周期CPU设计，实现的指令有：算术运算指令、逻辑运算指令、移位指令、比较指令、存储器读/写指令、分支指令、跳转指令、停机指令。(Simple single-cycle CPU design,The instructions implemented are as follows:Arithmetic operation instruction, logical operation instruction, shift instruction, comparison instruction, memory read/write instruction, branch instruction, jump instruction, stop instruction.)

have a good documenty

说明：  amba总线桥:ahb to asb!verilog hdl文档加代码，非常全，soc(amba bus bridge: ahb to asb! verilog hdl code for the document plus a very full, soc)

四进制计数器模块，使用VHDL语言编写，在ISE8.1中经过测试的模型-quaternary counter module, the use of VHDL language, in which ISE8.1 tested model

这是个双端口双端口ram的定义，当然读者在此基础上还可以扩充(This is a dual-port dual-port ram definition, of course, on the basis of the readers can also be expanded)

最新的CCSDS高光谱图像压缩算法标准的FPGA实现，用VHDL实现的。可参考。绝对物有所值，希望对你的设计有所帮助!

等精度测试频率计，包括程序源代码以及相关注释-Precision test frequency meter, etc., including source code and related comments ......

Verilog 写的HDMI接口源程序及说明文档(HDMI interface verilog code and specificaiton paper)

CAN VHDL Code. Behavioral implementation of CAN bus interface.