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5-15
用verilog语言实现基于DDS技术的余弦信号发生器,其输出位宽为16比特(Verilog language cosine signal generator based on DDS technology, the output bit width is 16 bits)
- 2013-04-18 22:58:05下载
- 积分:1
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可编程逻辑器件cpld与单片机双向通信的源程序
可编程逻辑器件cpld与单片机双向通信的源程序-Programmable logic device CPLD and MCU for two-way communication of the source
- 2022-01-25 20:21:15下载
- 积分:1
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内附多路选择器,74系列芯片VHDL源码,加法器,FIR,比较器等大量例子,对初学VHDL语言很有好处。可用maxplus,quartus,synplicity...
内附多路选择器,74系列芯片VHDL源码,加法器,FIR,比较器等大量例子,对初学VHDL语言很有好处。可用maxplus,quartus,synplicity等综合软件进行调试-contains multiple-choice, 74 chips VHDL source code, the adder, FIR, comparators, etc. are plenty of examples for beginners VHDL very good. Available maxplus, Quartus, synplicity integrated software debugging
- 2022-08-11 02:50:00下载
- 积分:1
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lab5
串口控制器,基于vivado软件下开发,包含代码及管脚分配文件(Serial port controller)
- 2017-12-07 16:40:56下载
- 积分:1
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mul
实现有限域中乘法,输入二个普通二级制数,输出在本原多项式的乘法结果(Achieve limited multiplication field, enter the number of two-tier system of two ordinary output in primitive polynomial multiplication results)
- 2014-01-12 22:52:38下载
- 积分:1
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MUX
说明: 用CASE实现4选1数据选择器 很实用 运用VERILOG(Using CASE to achieve 4 election 1 Data Selector practical use Verilog)
- 2008-09-11 11:37:35下载
- 积分:1
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mux_16bit_sign
16位有符号和无符号乘法器FPGA源代码(16-bit signed and unsigned multiplier FPGA source code)
- 2016-05-09 21:48:03下载
- 积分:1
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cnv_enc_modify
卷积码(2,1,7)编码器,一个输入,两个输出(Convolution code (2,1,7) encoder, an input and two outputs)
- 2015-05-20 10:21:56下载
- 积分:1
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LAB22
应用verilog编程语言控制VGA显示屏显示一幅图片。(Application verilog programming language control VGA display shows a picture.)
- 2016-10-27 16:30:12下载
- 积分:1
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ADS7844 AD转换芯片的VHDL控制器
ADS7844 AD转换芯片的VHDL控制器-ADS7844 AD converter chip VHDL controller
- 2022-02-02 13:25:44下载
- 积分:1