最近组长给分配的任务，这几天一直在做，比较郁闷的是用的器件是XC400XL系列的，只有ISE4.1支持，用惯了7.1i的我还是要适应一阵子（关键4.1是一个试用...

Pipeline processor verilog components

一个基于FPGA用verilogHDL设计的bayer格式转RGB格式的模块，本人设计(a code used for bayer_3RGB_interpolation ,which based on FPGA by verilogHDL)

SoC sample Code using Altera Xcaliber, good usefull SoC.

ANALYSIS OF ALL GATESS

该程序描述了运用FPGA进行控制的S形曲线和其他传统加减速控制曲线方法的控制曲线比较研究。(This program is compiled in matlab circumstance。Describing the approach of S-curve control method in FPGA in machine controlling.)

verilog开发FPGA，实现RS485串口通信(RS485 driver for FPGA )

基于FPGA数字频率计，VHDL，quartus，8位频率显示，精确度高

基于BCD码的十进制ALU设计，可实现加减乘除的功能(BCD to decimal ALU based design can achieve the arithmetic function)

数字滤波器包含IIR数字滤波器和FIR数字滤波器。本设计的工作主要是Labview软件部分，包括信号生成模块、滤波模块、显示模块的设计(IIR digital filter comprises a digital filter and FIR digital filters. The design work is mainly Labview software parts, including signal generation module, filter module, display module design)

QFSK的调制与解调，用C写的主程序，汇编写的调制与解调的子程序(QFSK the modulation and demodulation, with the main program in C, compile writing, the modulation and demodulation of the Subprogram)