DDs直接数字频率合成器的源代码，其中包括采用IP核和普通两种方式...

浙江大学体系结构实验课代码 实现5级流水线带有停顿，旁路和控制竞争的处理。(Experimental Architecture, Zhejiang University course code with a pause 5-stage pipeline, bypassing the treatment and control of competition.)

Parallel to Serial converter Module

以ISE为开发环境，Verilog语言编写程序。功能：FPGA控制 LCD_1602动态显示秒表(In the development environment of ISE, Verilog language is used to write programs. Function: LCD_1602 dynamic display stopwatch controlled by FPGA)

详细讲解时序约束培训教材，有利于更好对时序约束的理解(Timing constraints elaborate training materials, facilitate better understanding of the timing constraints)

ＦＰＧＡ设计中的一些经典例子对学习ＦＰＧＡ的人会有帮助-FPGA design of some of the classic examples of people learning FPGA would be helpful

上海交通大学电子信息与电气工程学院VHDL经典教程-Shanghai Jiaotong University Electronic Information and Electrical Engineering, Institute of Classical VHDL Tutorial

ALTERA NIOS处理器，用VHDL在QUARTUS下编写，用NIOS SHELL调试通过，实验LCD液晶显示-Altera NIOS processor, using VHDL in QUARTUS prepared with NIOS SHELL debug through experimental LCD

利用ITU656接口传输数据流的方法!已得到应用!(ITU656 interface transfer data streams using the method! Has been applied!)

在QuartusII下进行编译和仿真的时候,会出现一堆warning,有的可以忽略,有的却需要注意-QuartusII warning solving

Sample behavioral waveforms for design file sin_rom.vThe following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design sin_rom.v. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 3F0, 3F1, 3F2, 3F3, ...). The design sin_rom.v has one read port. The read port has 1024 words of 10 bits each. The output of the read port is unregistered. Fig. 1 : Wave showing read operation. The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until