The use of long

DES加密算法的VHDL实现,采用流水线技术实现(The VHDL implement of DES encrypt algorithmic)

VHDL 洗衣机程序，可实现定时、报警、洗衣，脱水等等功能。底层为VHDL文件，顶层为电路图连接

BCH3.c,提供m<21以下的所有码长的BCH编解码模块。以供大家参考。谢谢(BCH encoder&decoder GF(2^m) m<21)

基于FPGA的1602时钟显示,驱动1602显示时钟,矩阵键盘调时(1602 FPGA-based clock display, clock display driver 1602, when the transfer matrix keyboard)

数字系统设计报告，多功能电子钟，显示年月日星期时分秒，及校时等功能(Digital system design report, multi-functional electronic bell, show date when the minutes and seconds a week, and school functions when)

this program get 20 point from user and draw functions.

SDRAM控制器源码，内含完整的控制器verilog源代码和测试代码，超值哈。-This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1.

基于XIlinx ISE，用Verilog语言实现3分频电路，适合初学者(Based XIlinx ISE, Verilog language using the frequency dividing circuit 3, suitable for beginners)

乘法器的vhdl语言描述.本人调试已经通过-Multiplier described in VHDL language. I have been through the debugging

基于FPGA芯片，在Nios II IDE软件的开发环境下写的NIos II 软核uart源代码！-Based on FPGA chip, the Nios II IDE software development environment written in NIos II soft-core uart source code!