The use of long

基于IEEE802.11n标准,采用verilog语言设计的(2,1,7)卷积码viterbi译码器,支持1/2,2/3,3/4,5/6四种码率的译码,以测试无误(IEEE802.11n standard Verilog language design (2,1,7) convolutional code viterbi decoder support 1/2, 2/3, 3/4, 5/6 four bit rate decoding to test and correct)

这是用VHDL编写的译码程序,程序简单易懂-VHDL prepared decoding procedures that are simple to understand

ALTERA PCIE FPGA开发板（EP4C平台）DDR2内存测试代码(ALTERA PCIE FPGA development board (EP4C platform) DDR2 memory test code)

RISC-DSP组合处理器设计优化[1].-RISC-DSP processor design portfolio optimization [1].

verilog实现的“六进制约翰逊计数器”。(verilog implementation of the " six hexadecimal Johnson counters." )

60进制计数器,（由一六进制和十进制连线组成）(60 binary counter (hexadecimal and decimal by a connection form))

精通VerilogHDL：IC设计核心技术实例详解-proficient VerilogHDL : IC design example explanation of the core technology

simple code based on verilog shifter , cla ,clg , ALU , PC

此代码是SPI接口的Master的Verilog源代码，经上板测试是没有问题的，请大家放心使用 (This code SPI Interface Master of Verilog source code, there is no problem on board test, please rest assured to use)

CAN总线的数据采集，FPGA到USB。verilog hdl语言。(CAN bus data acquisition, FPGA to the USB. verilog hdl language.)