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本实验实现PS/2接口与RS
本实验实现PS/2接口与RS-232接口的数据传输,
PS/2键盘上按下按键,可以通过RS-232自动传送到主机的串口调试终端上(sscom32.exe);
并在数据接收区显示接收到的字符。
串口调试终端的设置:波特率115200,一个停止位,无校验位。-Realize this experiment, PS/2 interface with RS-232 data interface, PS/2 keyboard to press the button, through RS-232 automatic transmission to the host serial debug terminal (sscom32.exe) and data receiving display received characters. Serial debug terminal settings: 115200 baud rate, one stop bit, no parity bit.
- 2022-08-08 00:57:00下载
- 积分:1
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Regs
说明: 一个小寄存器堆,使用参数化编程,附有仿真代码,可直接在vivado(2018.2版本及以后)上运行(A small register heap, using parametric programming)
- 2019-04-03 14:19:55下载
- 积分:1
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PID-algorithm
PID算法控制点击速度,PWM脉宽调制方法(PID algorithm to control the motor
Speed)
- 2012-03-22 12:23:09下载
- 积分:1
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dianzhen
fpga实验板上16*16点阵显示汉字的程序-翻译结果fpga实验板上16*16点阵显示汉字的程序(Experimental fpga board 16* 16 dot matrix display Chinese program- translation results fpga experimental board 16* 16 dot matrix display Chinese characters in the program)
- 2013-12-24 16:28:00下载
- 积分:1
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divisor
Time divisor vhdl code
- 2009-06-02 21:31:05下载
- 积分:1
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- 2022-07-05 02:24:05下载
- 积分:1
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fpga
说明: 中科院FPGA的课件!纯英文,比较简单,适合刚刚接触FPGA的小白!(Chinese Academy of Sciences FPGA courseware! Pure English, relatively simple, suitable for Xiaobai who just came into contact with FPGA!)
- 2020-03-19 14:19:16下载
- 积分:1
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dds32_1
说明: 频率合成器实例模块设计。频率分辨率为32位DDS的VHDL程序(Frequency synthesizer module design example. 32-bit DDS frequency resolution of the VHDL program)
- 2011-04-14 13:45:22下载
- 积分:1
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24x24-booth
可用的24位x24位的booth乘法器的verilog代码(24X24 booth muplily)
- 2011-06-09 17:59:26下载
- 积分:1
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用verilog写的,基于查表法实现的LOG10运算器,在Altera FPGA中应用。...
用verilog写的,基于查表法实现的LOG10运算器,在Altera FPGA中应用。-It is a verilog design of LOG10 calculation unit, which is based on LUT arithmatic. And it is applicated in Altera FPGA.
- 2022-08-17 06:30:14下载
- 积分:1