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Based on the VHDL language for selecting the three sequences, you can have a cyc...
基于VHDL语言的3级序列的产生,可以循环产生周期为7的m序列
-Based on the VHDL language for selecting the three sequences, you can have a cycle for cycle 7 m sequence
- 2023-08-16 17:00:04下载
- 积分:1
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verilog full case and paralel case directive usage
verilog full case and paralel case directive usage
- 2022-05-28 07:00:24下载
- 积分:1
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用VHDL和verilog实现的四人抢答器
用VHDL和verilog实现的四人抢答器-using VHDL and verilog realization of four Responder
- 2023-07-17 00:15:04下载
- 积分:1
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2003101190493221
还好用,大家一起来看下,不错的图书管理软件啊 ,呵呵(Fortunately with, everyone look, the good library management software, ah, huh, huh)
- 2010-09-14 13:08:40下载
- 积分:1
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EDA VHDL modules commonly used procedure, the time
EDA中常用模块VHDL程序,不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ,25分频=2HZ,10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time- with a counter by the external input is required when the sub-frequency functions. Frequency Divider FENPIN1/2/3 (50 1HZ frequency = 25 = 2HZ-frequency, frequency = 10 points Stripper. A slight change in procedure can be realized)
- 2022-07-02 21:52:46下载
- 积分:1
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用FPGA 是先键盘的程序,is good for you
用FPGA 是先键盘的程序,is good for you -FPGA is the first keyboard to use the procedure, is good for you
- 2023-08-22 22:30:03下载
- 积分:1
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可配置CRC参考设计 xilinx提供的VHDL
可配置CRC参考设计 xilinx提供的VHDL-configurable CRC reference design for Xilinx VHDL
- 2022-01-23 10:27:39下载
- 积分:1
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DDs直接数字频率合成器的源代码,其中包括采用IP核和普通两种方式...
DDs直接数字频率合成器的源代码,其中包括采用IP核和普通两种方式-DDS Direct Digital Synthesizer source code, including the use of IP core and the general two ways
- 2022-01-23 11:02:21下载
- 积分:1
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Verilog
32位存储器Verilog附带test文件,可以在modulesim仿真
还有加法、减法器,译码器等常用Verilog器件,都附带仿真test。(Memory test with Verilog)
- 2010-07-17 17:20:00下载
- 积分:1
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全部通过,是我的精心设计,完全满足初学者的要求。
全部通过,是我的精心设计,完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.
- 2022-03-02 01:44:58下载
- 积分:1