UART receiver and transmitter using vhdl

说明：  LDPC码的FPGA实现，用verilog语言编写(FPGA implementation of LDPC code, written in Verilog language)

由VHDL 语言实现的数控分频 利用的是QUARTUES环境已经得到验证-By the NC VHDL language is the use of sub-frequency QUARTUES environment has been tested

说明：  简单的一个Verilog小程序，适合刚接触的人群(A simple Verilog small program, suitable for people just contact)

基于verilog的2FSK调制程序，simulink仿真通过(2FSK modulation program based on Verilog, Simulink simulation passed)

介绍了硬件语言的仿真软件modelsimse的操作是使用方法，可以为入门的参考资料-Introduction of the hardware language modelsimse operation simulation software is to use the method of reference for the entry

说明：  八相移键控调制的Verilog程序，给出了各个子模块的程序，实现了信号调制。(Eight-phase shift keying modulation of the Verilog program, each module is given the procedures, the signal modulation.)

FPGA-CPLD实习计数器7段数码管控制接口设计与LED显示控制，FPGA译码(FPGA-CPLD internship counter 7-segment LED control interface design and LED display control, FPGA decoder)

AES 128 bit with various device interface on FPGA

该程序是一个可完成订制化的SPI双向总线接口，时钟相位、极性，以及分频比全部可通过寄存器进行配置，已经在ISE下通过综合，占用资源少，强烈推荐 (The program is a complete custom of SPI bidirectional bus interface, clock phase, polarity, and the divider ratio can all be configured through the register, has been in the ISE through an integrated, small footprint, it is strongly recommended)

离散余弦变换及反离散余弦变换的HDL代码及测试文件。包括VHDL及Verilog版本。可用途JPEG及MEPG压缩算法。-Discrete cosine transform and inverse discrete cosine transform of the HDL code and test files. Including VHDL and Verilog versions. And MEPG can use JPEG compression algorithm.