CH2CH1VHDL 数字电路参考书所有程序4

ＡＤ转换代码，主要练习，没有具体的功能可以实现的，因为只是一部分(AD conversion code, practice, no specific function can be realized, because only part)

十进制计算机，实现十进制计数功能，简单可靠(vhdl)

本代码来自老师指导，自己编写，可以修改交通灯的时间

实现psk调制解调，vhdl代码，仿真文件也有(psk shixian tiaozhiyujietiao)

电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)-Electronic Design Competition works _ audio signal source analyzer FPGA (first prize)

modsim仿真必备，可以帮助你解决很多你对软件不熟悉的问题！-Simulation modsim necessary, I can help you solve many of the software you are not familiar with the problem!

说明：  用VHDL语言仿真乘法器设计, 经过modelsim仿真， synplify综合，并下载进FPGA验证(Multiplier design using VHDL, simulation, after modelsim simulation, synplify synthesis, and downloaded into a FPGA verification)

一个2位的BCD码十进制加法计数器电路，输入为时钟信号CLK，进位 输入信号CIN，每个BCD码十进制加法计数器的输出信号为D、C、B、A和进位输出信号COUT，输入时钟信号CLK用固定时钟，进位输入信号CIN. (A 2-bit BCD code decimal adder counter circuit input as the clock signal CLK, a carry input signal CIN, D, C, B, A, and the carry output signal COUT, each BCD code decimal adder counter' s output signal, the input clock signal CLK Fixed clock, binary input signal CIN.)

ADC7606的驱动代码，采用verilog实现(ADC7606 driver code, using Verilog to achieve)

说明：  SDIO 接口，实现SD卡的控制器功能，带有详细的注释(SDIO Interface,to realize the controller of SD Card,and have detail description.)