登录
首页 » VHDL » SONY公司出品的黑白CCD(44万像素)ICX229的驱动信号产生程序

SONY公司出品的黑白CCD(44万像素)ICX229的驱动信号产生程序

于 2022-04-17 发布 文件大小:12.53 MB
0 243
下载积分: 2 下载次数: 1

代码说明:

SONY公司出品的黑白CCD(44万像素)ICX229的驱动信号产生程序-SONY company produced black-and-white CCD (44 megapixels) ICX229 the drive signal generation process

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core....
    用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.-algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company"s paid Multiplier ip core.
    2022-03-30 14:40:42下载
    积分:1
  • DE2 development company for the altera board SD_Card_Audio examples
    用于altera公司DE2开发板上SD_Card_Audio的实例-DE2 development company for the altera board SD_Card_Audio examples
    2022-12-25 12:55:03下载
    积分:1
  • ADPCM
    说明:  APPCM算法和AD/DA芯片驱动在CPLD中的实现,已在实际硬件中测试OK,quartus2环境(APPCM algorithm and AD/DA chip in the drive to achieve in the CPLD has been tested in actual hardware OK, quartus2 environment)
    2009-08-22 10:07:03下载
    积分:1
  • AXI总线接口控制代码
    本代码为简单AXI接口控制模块,具备数据的读写等传输功能,对总线传输学习者来说是很好的学习资料,可在此代码基础上进行更复杂功能接口的模块的开发。
    2022-08-15 09:53:12下载
    积分:1
  • Snacke
    基于NiosII系统的可以在DE2-115板子上运行的吞食蛇游戏!(可以使用RS2键盘进行控制)(DE2-115 board NiosII system swallowed snake game! , (RS2 keyboard control))
    2013-01-01 10:12:03下载
    积分:1
  • kt1
    基于FPGA的可控100进制可逆计数器,运行环境maxplus(Controlled 100 hex reversible counter FPGA-based operating environment maxplus)
    2012-05-17 12:19:54下载
    积分:1
  • AMBA-Bus_Verilog_Model
    说明:  该源码包是2.0版本的AMBA总线的Verilog语言模型,主要包括5个部分:AHB总线仲裁器,AHB-APB总线桥接器,AHB总线上从设备ROM模型,AHB总线上从设备RAM模型,参数定义。(This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.)
    2021-04-25 21:48:46下载
    积分:1
  • test2
    说明:  试用Verilog HDL语言,设计十进制计数器,将计数过程用一个数码管进行显示(0~9)。要求首先使用Modelsim软件进行功能仿真,然后使用Quartus软件综合,并下载到开发板进行电路功能测试。(Using Verilog HDL language, a decimal counter is designed. The counting process is displayed by a digital tube (0 ~ 9). It is required to first use Modelsim software for functional simulation, then use quartus software for synthesis, and download to the development board for circuit functional test.)
    2020-05-17 11:07:28下载
    积分:1
  • 自适应均衡器
    自适应均衡器
    2022-07-13 15:30:18下载
    积分:1
  • 双电梯控制器
    说明:  使用verilog实现的双电梯控制器,1-9层,仿真通过(a bi-elevator controller written in VerilgHDL, which has floor1-9, simulation passed)
    2020-06-17 11:44:27下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载