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function_automatic
Verilog使用automatic function的範例(Verilog example of the use of the automatic function)
- 2009-06-18 12:01:30下载
- 积分:1
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yuandaima
以GPS为时间基准,实现多传感器器数据同步采集,整合信息后发送 VERILOG语言编写 QUARTUS II环境(GPS-time basis, synchronized multi-sensor data acquisition, integration of information after sending VERILOG language environment QUARTUS II)
- 2014-10-12 19:15:45下载
- 积分:1
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lab8000
矩阵键盘扫描和led显示
这样子可以得到要输入的键码,并通过led显示出来(KEYBOARD AND DISPLAY LED)
- 2012-12-11 22:49:44下载
- 积分:1
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xilinx_dna_read
该模块已经成功运用在xilinx xc6slx45t,xc6slx75t多个产品中,经过实践证明,采用dna及其加密算法加密是一种成本低廉(无需另外加密芯片)可靠的加密手段。Xilinx Spartan-6 FPGA读取DNA数据并进行比较,产生比较结果信号输出。附带有xilinx DNA.ppt说明及调试注意事项。(The module has been successfully used in xilinx xc6slx45t, multiple xc6slx75t products, proven, and the encryption algorithm uses dna is a low-cost (no additional encryption chip) reliable means of encryption. Xilinx Spartan-6 FPGA reads the data and compare DNA to produce a comparison result signal output. Xilinx DNA.ppt comes with instructions and commissioning notes.)
- 2020-10-15 20:07:29下载
- 积分:1
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vedic_Code
vedic multiplication
- 2015-11-16 19:19:40下载
- 积分:1
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计时器程序设计
利用Quartus 综合简单的计时器功能,欢迎大家下载、参考。谢谢大家的支持!
- 2023-05-24 21:20:03下载
- 积分:1
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Mashayan
rebuild file in check for
- 2018-01-27 16:36:35下载
- 积分:1
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cn60
六十进制计数器用于计数等操作,代码的实现方式很简单(Six decimal counter for counting operation, the code is very simple implementations)
- 2014-12-10 10:10:50下载
- 积分:1
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bhas
this is a vhdl program...
- 2013-08-17 23:30:56下载
- 积分:1
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16个VHDL 编程实例
本文件夹包含了16个VHDL 编程实例,仅供读者编程时学习参考。 一、四位可预置75MHz -BCD码(加减)计数显示器(ADD-SUB)。 二、指示灯循环显示器(LED-CIRCLE) 三、七人表决器vote7 四、格雷码变换器graytobin 五、1位BCD码加法器bcdadder 六、四位全加器adder4 七、英语字母显示电路 alpher 八、74LS160计数器74ls160 九、可变步长加减计数器 multicoun
- 2022-06-19 01:26:50下载
- 积分:1