一般网站上都有i2c master模块的代码,但很少有slave的代码,这里就是slave的代码,非常有用....

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像基本操作,几何变换,直方图,灰度化处理等(System Generator based image processing engineering, multimedia processing FPGA implementation source code, the basic operation of the image, geometric transformations, histogram, gray processing)

quartusii 三分频电路，大家帮参考一下，有什么问题-one-third of quartusii frequency circuit, refer to U.S. help, have any problem

Learning Verilog Chinese Version Part 8

verilog语言设计的VGA驱动。在Quarus11.0下编译成功，并在Altera cyclone4开发板上测试OK(verilog language design VGA driver. In Quartus11.0 successfully compiled and Altera cyclone4 development board test OK)

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ladder IS PORT(clk,reset:IN STD_LOGIC;

通过CPLD将8位并行数据转换为串行数据并可以采用I2C方式与其他器件连接，可以用于MCU需要与提供I2C接口器件通信的场合。-through CPLD to eight parallel data into serial data and methods can be used I2C connections with other devices, which can be used to provide MCU with I2C Interface Communications occasions.

使用FPGA透过RS232与PC的作沟通，

verilog编写的SDRAM实验，有串口调试助手和相关资料！！！！！！！！！！！！！！！！！！！！！(Verilog prepared by the SDRAM experiment, a serial debugging assistant and related information!!!!!!!!!!!!!!!!!!!!!)

含移动储能的分布式电能优化调度，模型的处理与改进(Processing and improvement of distributed power optimization scheduling with mobile energy storage)

高速串行设计FPGA-GTX IP设置生成drp模块，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接(High-speed serial design FPGA-GTX IP setting generation drp module, dynamically configurable rate 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link)