完成的是RS422信号的计数功能，并产生一定的触发信号

VHDL与源代码包-and VHDL source code

模块化分散聚集 DMA 是连续或非连续的转移。如正常 DMA 或散点图聚集 DMA 配置的输入或输出的部分。

交通灯控制系统VHDL源码，用VHDL语言、MAXPLUS2环境设计实现(VHDL core)

The xapp851.zip archive includes the following subdirectories. The specific contents of each subdirectory below:   tl   - HDL design files   sim   - simulation files   synth - Synthesis related files   par   - Place/Route related files 以及DDR SDRAM控制器设置.pdf文件

DE2-70,NIOS reference file,

EV10AQ190A配置程序 EV10AQ190A configuration program(EV10AQ190A configuration program)

MX25L6445E开发时间，Verilog语言(MX25L6445E development time, Verilog language)

SEG7数码管显示示例程序，适用于ALTERA的CPLD(SEG7 digital display sample program of ALTERA CPLD)

介绍了在数字语音通信中, 利用在系统可编程技术和复杂可编程逻辑器件CPLD, 实现了数字语音的复接和分接 对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。实际应用结果表明, 系统工作稳 定可靠, 设计是成功的。(Describes the digital voice communications, the use of in-system programmable technical and complex programmable logic device CPLD, to achieve the digital voice multiplexer and demultiplexer for the single steady state in which the digital circuit and digital phase locked loop extraction bit synchronization signals are also carried out a detailed design specification. The practical application results show that the system works stable and reliable design is successful.)

用VHDL语言编写的实现8位数据的并串转换，可下载在FPGA中-VHDL language with the realization of an 8-bit data, and the string conversion, can be downloaded in the FPGA in