and VHDL source code

有用的数字钟设计文档，有秒表、闹钟等模块，希望对大家有用！(JUST LEARN FROM IT!!ENJOY!)

一个SDH中最基本传输模块STM-1的帧头检测器，verilog编程实现-A basic SDH transmission module STM-1 Header detector, verilog Programming

VERILOG HDL 实际工控项目源码 开发工具 altera quartus2-verilog HDL actual industrial projects source development tools altera quartus2

黑金FPGA助学版-tcl,包含开发板所有管脚。不需要再对板子管脚定义。AX301(Black Gold FPGA Student Edition-tcl, development board contains all the pins. No need for a board pin definitions. AX301)

这是一篇现代通信原理课程的作业报告.题目为几种时频分析方法比较及应用.详细介绍了短时傅里叶变换、小波变换、魏格纳—威利分布和Cohen类时频分布这4种典型时频分析方法,并作了比较(This is a modern communication Principle operating report. Entitled Comparison of several time-frequency analysis and 应用. 详细 Jieshao the short time Fourier transform, wavelet transform, Wigner- Willie distribution and frequency distribution of Cohen Lei This four kinds of typical time-frequency analysis method, and compared)

Link the VGA adapter located in the altera DE2board to a monitor

HDLC通信协议，FPGA实现，包含源文件和仿真测试文件。(HDLC comunication)

节约资源型 8位*8位 运算VHDL代码，采用串行运算，8 个时钟周期完成一次运算。QUARTUS下已验证(resource conservation-8* 8 Operational VHDL code, using serial computation. 8 clock cycles to complete an operation. QUARTUS has been under test)

一个FIFO产生程序，主要是一个格雷码的加法器(A FIFO generation process, is primarily a gray code adder)

Clock Divider, divfactor of 18