用VHDL语言编写的实现8位数据的并串转换，可下载在FPGA中

这是spi接口传输的一部分内容，本源码一共三部分，功能：spi接口的的实现即对外设的读写数据-This is the spi interface transfer part of the contents of a total of three parts of this source, function: spi interface that the realization of the read and write data to the peripheral

PCI Arbitor by VHDL -PCI Arbitor by VHDL

使用信号功率计算，检测信号是否到达。从而控制后续模块，以减小系统功耗。(Signal power calculation, the detection signal to reach. To control follow-up modules to reduce system power consumption.)

用verilog写的，基于查表法实现的LOG10运算器，在Altera FPGA中应用。-It is a verilog design of LOG10 calculation unit, which is based on LUT arithmatic. And it is applicated in Altera FPGA.

This code that genetes a square, sawtooth and a triangular waveform. It is useful for designing a function generator in VHDL.

SPI Verilog code with programmable clock

世界时钟，最简单的vhdl的fpga设计，是vhdl语言的入门级，jigon供参考娱乐

企业用verilog代码风格规范 本规范规定了IC设计项目开发过程中VerilogHDL源代码的编写总则、要求及模板文件。(Enterprises with verilog code style guide for the preparation of this specification General IC design project development process VerilogHDL source code, requirements and template files.)

采用quartus的数模转换模块，RTL电路图(DAC module, RTL circuit diagram)