键盘输入串口输出显示字符,通过串口显示键盘输入的字符

CH2CH1VHDL 数字电路参考书所有程序3-CH2CH1VHDL digital circuit reference all three procedures

具有多种功能的电子钟：闹钟，报时和修改，定时闹钟，报时时间，带闹钟，报时开关。-with multiple functions of electronic bell : alarm clock, timer and modification, regular alarm clock, timer, with alarm clock, timer switches.

TIMING LEARNING -TIMING LEARNING

altera remote updata cyclone5 平台例程，无nios核版本(altera remote updata cyclone5 platform routine do not use nios)

实现矩阵相乘，即点积运算，为VERILOG语言。可以根据自己的需要改变维数，采用了流水线的结构(Achieve matrix multiplication, ie dot product operations, for VERILOG language. You can change the dimension according to their needs, using a pipeline structure)

单相混合有源电力滤波器的设计与控制，在matlab中的仿真模型，功能效果很好。(The design and control of single-phase hybrid active power filter in matlab simulation model, the function works well.)

FPGA下PWM的Verilog 源码，含目标程序，可直接下载使用，可用在电机控制中-FPGA in Verilog source code under the PWM, including the target program, can be directly downloaded to use, can be used in motor control in

16*16点阵横向移动显示！采用QUARTUS II 9.0编译通过！(16* 16 dot matrix display lateral movement! Compiled by using QUARTUS II 9.0!)

buffer_display是4X4KEYPAD的输出显示模块。可以显示6个连续的按键-buffer_display is 4X4KEYPAD output module. It showed six consecutive Press

改进的DCT算法设计，veriloghdl实现-Improved DCT algorithm design, veriloghdl realize