键盘输入串口输出显示字符,通过串口显示键盘输入的字符

VDHL的简单DEMO演示，有利于初学者学习使用(VDHL simple demo DEMO will help beginners learn to use)

verilog语言实在点变换DFT源代码，可以配合软核或者其他CPU进行综合FFT变换，也可以单独使用生成module！(verilog language is point FFT transform source code, can tie in with the soft-core CPU, or other integrated FFT transform, it can be used to generate module!)

说明：  formality2016 userguide

eDP接口TFT-LCD显示驱动原码（verilog+c）(eDP Interface TFT-LCD display driver source code (verilog+c))

使用VHDL键盘扫描程序，可以稍微修改一下使用

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License

the basic system of nexys3(soft core)

说明：  对于一串二进制数前置零的计数的Verilog程序(For a string of binary zero count Verilog pre-procedure)

Verilog code for RS-(255,239) encoder.

十字路口交通灯的单片机控制源代码 红黄绿三灯 还有数码管时间显示(Intersection traffic lights SCM source code red yellow three lights and LED time display)