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ps2_lcd
此代码能够使得键盘控制液晶,实时的进行书写,按下Backspace清屏(This code enables the keyboard to control the LCD, in real-time writing, press Backspace clear the screen)
- 2013-01-27 11:04:40下载
- 积分:1
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这个RAR文件包含有关FPGA和CPLD的呈现。
This rar files contains the presentation about FPGA and CPLD .
- 2022-07-13 06:31:38下载
- 积分:1
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SPITX16
基于状态机的优秀SPI输出程序(以DAC7512为基础,可修改)(VHDL code about SPI)
- 2016-02-09 01:07:52下载
- 积分:1
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these files are written in verilog but i am uploading in text format
these files are written in verilog but i am uploading in text format
- 2023-08-21 20:45:02下载
- 积分:1
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FPGA-basedhardwareimplementationofneuralnetworks
基于FPGA的神经网络硬件实现中的关键问题研究,适合用fpga研究神经网络的工程人员参考(FPGA-based hardware implementation of neural networks in the study of key issues for research with neural networks fpga reference works)
- 2009-04-15 05:44:09下载
- 积分:1
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cpu8bit
这是一个计算机组成原理综合性实验:设计8位cpu。该cpu是8bit的代码,包含有4个寄存器,一个存储器,还有alu以及控制器。一共可以实现16条指令。(This is a computer composition principle of comprehensive experiment: Design 8 cpu. The cpu is 8bit code contains four registers, a memory, as well as alu and controllers. A total of 16 instructions can be achieved.)
- 2020-07-01 08:40:01下载
- 积分:1
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SR_DDS
DDS信号源设计,有正弦波,方波,三角波,AM波,FM波,还有PSK,FSK,16QAM等多种信号产生。(DDS signal source design, there are sine, square wave, triangle wave, AM wave, FM wave, as well as PSK, FSK, 16QAM and other signal generation.)
- 2016-03-20 22:04:51下载
- 积分:1
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AD_100k
ADC Reference code!Clock 100kHz
- 2020-06-24 10:40:02下载
- 积分:1
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sobel
在FPGA中,采用verilog HDL语言实现图像处理算法sobel,仿真实验通过(In the FPGA using verilog HDL language image processing algorithms sobel, simulation experiment)
- 2021-01-15 20:58:46下载
- 积分:1
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第七次课--视频图像DCT处理及水印嵌入
熟悉IIC协议总线协议,采用IIC总线对图像采集传感器寄存器进行配置,并转换为RGB565格式。
利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。
利用 SDRAM 接口模块的设计,实现了刷新、读写等操作;为提高SDRAM 的读写带宽,均采用突发连续读写数据方式;并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。
利用双线性插值方法实现对图像640×480到1024×768的放大操作。
完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format.
Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface.
With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA.
The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768.
Complete the VGA display interface design.)
- 2020-06-25 04:00:02下载
- 积分:1