ADS7870 Serial ADC Interface Using a CPLD

可以产生正弦波，三角波、锯齿波、方波，要求频率1Hz-100kHz，步进1Hz，具有自动扫频功能； 正弦波的相位可调，方波的占空比可调； (Can generate sine wave, triangle wave, sawtooth wave and square wave, the required frequency of 1 hz- 100 KHZ, step 1 hz, with functions of automatic frequency sweep The phase adjustable sine wave, square wave duty ratio is adjustable )

VHDL 基于cpld EPM570的DA转换代码(VHDL CPLD EPM570 the DA conversion code based on)

基于FPGA的门级逻辑实现快速乘法运算的verilog源程序。-FPGA-based gate-level logic implementation of rapid multiplication of the verilog source.

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像边缘提取(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image edge extraction)

freeDev数字应用开发板中的VGA控制器的IP核的verilog实现-freeDev digital application development board of the VGA controller IP core implementation of the verilog

说明：  汉明编码和解码的硬件描述语言（verilog），其被编解码的数据为M序列。 建议运行软件为Quartus.(failed to translate)

circuit design with VHDL e-book MIT Press....

自己搜集的一些FPGA指南教程，包括一些高工们的经验之谈、设计原则，目前正在学习，有一定帮助，分享给大家(Gather their own of some FPGA guide tutorial, including some senior engineers are the voice of experience, design principles, are learning to have some help, to share to everyone)

FPGA 数码管接口例化编程，学习初级入门verilog编程技术(FPGA 数码管接口例化编程)

eda技术与vhdl课件,很经典的学习课件-VHDL EDA technology and courseware, it is a classic learning courseware