Source code for asyn_fifo using verilog language.

这是可编程逻辑器件（CPLD）初学者的入门级文章，仅供参考。-This is the programmable logic device (CPLD), the entry-level beginners articles for reference purposes only.

sram 6bit仿真模型，verilog编写(sram 6bit simulation model, verilog prepared)

this a verilog code about serial transmit receive.-this is a verilog code about serial transmit receive.

说明：  利用FPGA实现对外设按键的控制，例如用户库用按键控制跑马灯的效果(FPGA is used to realize the control of external keys, such as the effect of user database using keys to control the running horse lamp)

shift example for verilog

thesis about design and implementation neural network using FPGA

bios spi flash acer 5740g

这是一个vhdl代码的进位选择加法器及其工作100%。

说明：  OFDM信号的发送与接收 ，需要自取。时域图，模糊图，削峰。(Sending and receiving of OFDM signal)

说明：  verilog编写的RS485读写驱动程序(RS485 read-write driver written by Verilog)