Source code for asyn_fifo using verilog language.

VC++6.0软件生成Altera公司FPGA内部存储器ROM初始化数据mif格式文件。方便通过QuartusII导入波形等参数。强调这个是例子，生成的是一个定点的正弦数据表文件，需要用到的请自行修改源代码。(This software generates internal memory ROM initialization mif format data file for FPGA product by Altera. Facilitate the passage of the waveform parameters such as import QuartusII)

This is a simple example of FIFO(first in and first out) module written in verilog code(This is a simple example of FIFO (first in and first out) module written in verilog code)

FPGA based design and Implementation of Advanced Encryption Standard

ＦＰＧＡ在通信上的运用：基于VHDL的帧同步程序(Application of FPGA in communication: Based on VHDL frame synchronization procedures )

I2C EEPROM 存取源碼, 通用ATMEL(I2C EEPROM read/write)

基于Matlab的FPGA数字半带滤波器设计(Matlab-based FPGA digital half-band filter design)

DS18B20温度传感器的基于FPGA的编程通信，使用VHDL语言(DS18B20 temperature sensor based FPGA programming communication with VHDL)

自动化仿真平台的搭建使用代码，经过具体的仿真和优化，发现代码完全可用(The automated simulation platform is built using code, and after specific simulation and optimization, it is found that the code is fully available)

针对串行存储器M25P80应用的verilog程序-M25P80 serial memory for applications Verilog program

LED灯、跑马灯的显示源程序，包括对代码的说明(Display source code LED lights, marquees, including the code specification)