Source code for asyn_fifo using verilog language.

设计含异步清零和同步时钟使能的加法计数器-Clear design with asynchronous and synchronous clock so that the adder counter

计算机组成原理的CPU实验，基于quartus平台(CPU experiment of computer organization principle, based on quartus platform)

印制线路板设计经验点滴-Printed Circuit Board Design Experience

FPGA做VGA通讯的详细资料，我找了很久才收集起的，很有用，可供初学者学习实用-FPGA to do VGA communication details, I am looking for a long time before starting the collection, very useful for beginners to learn practical

说明：  一个简单的键盘接口模块程序，对键盘输入的数据和时钟信号进行过滤。过滤后的数据信号PS2Df将被送入两个11位移位寄存器中(A simple keyboard interface module program filters keyboard input data and clock signals. The filtered data signal PS2Df will be fed into two 11-bit displacement registers.)

Xilinx ISE 8.2i的license-Xilinx ISE 8.2i s license

该模块实现一个寄存器堆的操作，其中前16个仅主机能写，规给为32-bit×32。后16个仅Micorblaze能写。读取没有限制。如果双方同时对同一地址进行读写操作，读回的数将是全1。(This module implement a register file of the operation, of which the first host 16 is only able to write rules to the 32-bit × 32. Micorblaze only 16 after the write. There is no limit to read. If the two sides at the same time to read and write operations to the same address, read back would have been a full one.)

用CPLD驱动数码管，实现从0000计到9999，数码管是用动态显示，程序用VERILOG完成的-CPLD drives with digital control, of from 0000 to 9999, digital control is a dynamic display, the program completed with VERILOG

出租车记价器，使用vhdl语言编写的源码及其仿真。-Taxi price of devices in mind, use the source code written in vhdl and simulation.

同步FIFO功能，verilog语言描述，通过了modelsim 6.0 仿真，Quartue综合-Synchronous FIFO function, verilog language described by the modelsim 6.0 simulation, Quartue integrated