简易环形FIFO的设计、简单异步串行通信接口设计等

FPGA控制的SRAM接口不分的设计-FPGA-controlled SRAM interface design, regardless of

一个比较有参考价值的sram IP核，对SOPC感兴趣的人士有一定的指导意义！该程序是采用avalon总线，可以直接内嵌进SOPC Builder。-A comparison reference value has sram IP core, on the SOPC interested people have a certain guide! The procedure is used avalon bus, can be directly embedded into the SOPC Builder.

DESCRIPTION OF FULL ADDER

HDL example source code 2/5 dff_en

网上流传的用来实现FPGA驱动VGA，从而实现一个pingpong小游戏的源码，实测可用。(a program embedded in a FPGA in order to drive the VGA and realize a little game named pingpong. tested.)

FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation

BT656 时序, 逐行, 分辨率1280*960@25Hz(BT656 time series, row by row, resolution 1280*960@25Hz)

用verilog实现对三个16位数进行相加乘法器(Three 16-digit sum of the multiplier Verilog)

vga 测试代码，可以显示任意彩条，棋盘，花纹(VGA test code, can display any color bar, chess board, decorative pattern )

pc与fpga之间通过千兆以太网交换机实现网络通信(Network communication between PC and FPGA via Gigabit Ethernet switch)