包括各种类型存储器的VHDL描述，如FIFO，双口RAM等

基于FPGA芯片，在Nios II IDE软件的开发环境下写的NIos II 软核uart源代码！-Based on FPGA chip, the Nios II IDE software development environment written in NIos II soft-core uart source code!

HDB3编码通过verilog实现，通过modelsim仿真(HDB3 coding is implemented by Verilog and simulated by Modelsim)

LCD 驱动的IPCORE，可用于alteraFPGA(LCD driver IPCORE, can be used to alteraFPGA)

说明：  ZYNQ中 PS 端 CAN接口的基本使用方法，并通过 CAN接口实现与 PC 端 CA N调试软件之间的数据接收和发送(The basic use method of PS end can interface in zynq, and the data receiving and sending with PC end can debugging software through can interface)

实现任意倍数的倍频,帮助大家解决VHDL倍频问题,(The realization of arbitrary multiples of the octave, octave VHDL help people solve problems,)

Verilog 下脉冲发生器的源代码，可用于模拟三相交流电过零点，主要用于调试一些类似SVC（无功补偿）控制器的一些算法-Pulse generator under the Verilog source code, can be used to simulate three-phase alternating current zero-crossing point, mainly for debugging similar SVC (reactive power compensation) controller of a number of algorithms

本代码主要功能是PPM解码，采用Verilog语言，通过移位寄存器和组合电路实现解码。(The main function of this code is PPM decoding.)

基于VHDL语言的设计8位CISC微处理器实例-VHDL design language based on 8-bit CISC microprocessor examples

this is the vhdl code for the arithmetic logic unit.enjoy!

用VerilogHDL编写的，一个占空比为50％的6分频电路-prepared using Verilog HDL, a 50% duty cycle for the six sub-frequency circuit