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基于FPGA芯片,在Nios II IDE软件的开发环境下写的NIos II 软核uart源代码!...
基于FPGA芯片,在Nios II IDE软件的开发环境下写的NIos II 软核uart源代码!-Based on FPGA chip, the Nios II IDE software development environment written in NIos II soft-core uart source code!
- 2022-03-12 11:39:10下载
- 积分:1
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HDB3modelsim
HDB3编码通过verilog实现,通过modelsim仿真(HDB3 coding is implemented by Verilog and simulated by Modelsim)
- 2020-06-18 05:20:02下载
- 积分:1
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lcd-ip-core
LCD 驱动的IPCORE,可用于alteraFPGA(LCD driver IPCORE, can be used to alteraFPGA)
- 2011-02-15 11:34:38下载
- 积分:1
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CAN
说明: ZYNQ中 PS 端 CAN接口的基本使用方法,并通过 CAN接口实现与 PC 端 CA N调试软件之间的数据接收和发送(The basic use method of PS end can interface in zynq, and the data receiving and sending with PC end can debugging software through can interface)
- 2020-04-03 16:41:52下载
- 积分:1
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beipin_test
实现任意倍数的倍频,帮助大家解决VHDL倍频问题,(The realization of arbitrary multiples of the octave, octave VHDL help people solve problems,)
- 2021-03-24 17:19:14下载
- 积分:1
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Verilog 下脉冲发生器的源代码,可用于模拟三相交流电过零点,主要用于调试一些类似SVC(无功补偿)控制器的一些算法...
Verilog 下脉冲发生器的源代码,可用于模拟三相交流电过零点,主要用于调试一些类似SVC(无功补偿)控制器的一些算法-Pulse generator under the Verilog source code, can be used to simulate three-phase alternating current zero-crossing point, mainly for debugging similar SVC (reactive power compensation) controller of a number of algorithms
- 2023-06-15 23:20:03下载
- 积分:1
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PPM解码器
本代码主要功能是PPM解码,采用Verilog语言,通过移位寄存器和组合电路实现解码。(The main function of this code is PPM decoding.)
- 2020-12-10 18:29:19下载
- 积分:1
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VHDL design language based on 8
基于VHDL语言的设计8位CISC微处理器实例-VHDL design language based on 8-bit CISC microprocessor examples
- 2023-06-06 01:10:04下载
- 积分:1
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alu
this is the vhdl code for the arithmetic logic unit.enjoy!
- 2013-08-22 18:51:35下载
- 积分:1
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用VerilogHDL编写的,一个占空比为50%的6分频电路
用VerilogHDL编写的,一个占空比为50%的6分频电路-prepared using Verilog HDL, a 50% duty cycle for the six sub-frequency circuit
- 2023-06-23 12:25:03下载
- 积分:1