This is a simple routine FPGA is mainly based on FPGA

维特比译码，卷积编码，verilog编写，2,1,2编码(Victor than decoding, convolution code, verilog write, 2,1,2 coding )

一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了在Altera公司的ep1c20 FPGA的位码文件和配置文件，可以直接下载使用！-A VHDL design with the use of powerful 32-bit CPU, this document contains Altera Corporation in the ep1c20 FPGA code and configuration files, you can direct download!

The objective of this project is to design and implement the controller for an electronic safe. You will interface a 16-button keypad to the NIOS boards. The combination code of the safe will be the last

vhdl code for GIF Image Viewer

I2C 控制器的 Verilog源程序2(I2C controller Verilog source 2)

Package include hardware implementation of Lz77 algorithm

ML605评估板上的流水灯，可以实现每隔0.16秒进行+1操作 #include #include #include #include #include int main() {   char a[] = "-100" ;   char b[] = "123" ;   int c ;   c = atoi( a ) + atoi( b ) ;   printf("c = %d ", c) ;   return 0;

《Verilog HDL 程序设计教程》2-"Verilog HDL Design Guide," 2

基于verilog语言的差分曼彻斯特编码，内包含数据的采集，CRC校验（8位），和编码，输出。附有完整的工程文件。可直接调用modelsim仿真。(Based on differential Manchester encoding verilog language, and contains data collection, CRC check (8), and coding. With complete project file. Modelsim simulation can be called directly.)

一第二个计时器为斯巴达 6 fpga-结构设计的