This is a simple routine FPGA is mainly based on FPGA

本文以FPGA为硬件平台，基于EDA工具QUARTUSⅡ为软件平台上对HDB3编/译码进行实现。由于在EDA的软件平台QUARTUSⅡ上不能处理双极性的信号，因此对HDB3码的编/译码的实现分为：软件部分和硬件部分。软件部分是基于QUARTUSⅡ的平台上对输入的码元进行编码和译码，通过系统仿真，验证了HDB3码的编译码的正确性；硬件部分采用CD74HC4052双四选一的数模选择器实现单极性到双极性的转换；采用AD790和SE5539实现双极性到单极性的转换。最后，通过仿真，验证了方案的正确性。

vhdl经典源代码――LCD控制，入门者必须掌握-vhdl classical source code-- LCD control, beginners must master

这是我自己写的4位并转串ISE代码，在xilinx Spartan3E 上已经调试成功，拿出来与大家分享！-that I wrote four string and turn ISE code In xilinx Spartan3E debugging has been successful, with the show to share with you!

说明：  Verilog 入门,如果你要很了解Verilog你不用先谖完一本厚厚的书还弄不清楚Verilog到底在干啥事,这份资料有助於快速了斛Verilog(Verilog Basic, If you try very hard to understand verilog by read a thick book, try read this first you will get a quick understanding of verlog.)

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity song is    port(clk_4MHz,clk_4Hz:in std_logic;      ----预置计数器和乐谱产生器的时钟         digit:buffer std_logic_vector(6 downto 0);  ----高、中、低音数码管指示         zero:out std_logic_vector(4 downto 0);     ----用于数码管高位置低  

通过PC串口调试助手向MINI板发数据（HEX），在数码管显示接收到的数据，并回传给PC(The debugging assistant sends data (HEX) to MINI board through PC serial port, displays the received data in the digital tube and sends it back to PC)

实现beep发出1234567的音乐声音-beep 123456

usb3.0 物理层仿真，verilog编程(Start the physical simulation)

Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3* Double binary, DVB-RCS code* Soft Output Viterbi Algorithm* M yHDL cycle/bit accurate model* Synthesizable VHDL model

vhdl,无进位同步计数器，完成6进制加，输出6进制序列数-vhdl, non-binary synchronous counter to complete the six binary Canada, output 6, the number of binary sequences