带load、clr等功能的寄存器

改变学习板上的2个电位器对应的2段模拟输入，实现模拟输入，学员观察数码管的数字变化情况,通过改D[4]的值，实现模拟输出.(Changing the learning board two potentiometers corresponding paragraph 2 analog inputs, analog inputs, digital tube digital trainees observe the changes, by changing D [4] value for analog output.)

说明：  运用Verilog 语言进行数字积分法，将X轴和Y轴进行插补运算。(Verilog language using digital integration method, the X axis and Y axis interpolation operations.)

传感信号无线数字传输系统的设计与实现.kdh(err)

FPGA，VHDL语言 ：分频1S 8位流水灯，适用于所有FPGA芯片，VHDL源程序！！(FPGA, VHDL language: divide-1S 8 light water, and apply to all FPGA chip, VHDL source code! !)

FPGA SDI 输入，HDMI输出例程(FPGA SDI_IN,HDMI_OUT)

-- M68008 Address Decoder -- Address decoder for the m68008 -- asbar must be 0 to enable any output -- csbar(0) : X"00000" to X"01FFF" -- csbar(1) : X"40000" to X"43FFF" -- csbar(2) : X"08000" to X"0AFFF" -- csbar(3) : X"E0000" to X"E01FF" -- download from www.pld.com.cn & www.fpga.com.cn --- M68008 Address Decoder-- Address decod er for the m68008-- 0 asbar must be to enable any o utput-- csbar (0) : X "00000" to X "01FFF"-- csbar (1) : X "40000" to X "43FFF"-- csbar (2) : X "08000" to X "0AFFF"-- csbar (3) : X "E0000" to X "E01FF"-- download from www.pld. com.cn

用硬件描述语言编程实现减法器,实现两个操作数的减法-Using hardware description language programming subtraction, and the achievement of the two operands of the subtraction

its a verilog code for microcoded tb

ad9850函数发生器 MSP430单片机驱动程序 扫频 DDS(AD9850 DDS)

CH2 VHDL 数字电路参考书所有程序2-CH2 VHDL digital circuit two reference books all procedures