implementation of fft core using vhdl

利用LPM_MUIT宏模块设计一个四位数据乘法器(Use LPM_MUIT macro module design a four data Multiplier)

60进制减法 相比较 代码效率高 可以进行级联-60 compared to 229 subtraction efficient code can be concatenated

简单电子玩具的感知模块程序设计,通过外部输入信号改变内部信号.从而改变玩具的状态-simple electronic toys perception module programming, through external input signal a change in the internal signal. In order to change the state of toys

一个双向总线的vhdl实现-a two-way bus VHDL achieve

本设计是设计了一个4位全加器的内容，是由4个一位全加器串联而成的(The design is to design a full adder 4 content, is one of four full adder in series from the)

FPGA开发必备工具书，适合初学者。语法、范例讲的都很详细，是一部不错的工具书。(Verilog hardware description language Fourth Edition)

篮球24s计时。计时器递减计数到零时，数码显示器显示‘0’并停止，同时发出报警信号(basketball 24 seconds)

FPGA实现四位数与四位数乘法，有仿真波形，合理利用FPGA资源(Four-digit and four-digit multiplication is realized by using FPGA. It has simulation waveform and makes rational use of the resources of the FPGA.)

利用FPGA实现QPSK数字调制。编程采用Verilog HDL语言。(By using the FPGA realization of QPSK digital modulation. Use Verilog HDL language programming. )

实现图像的中值滤波功能，文件里有效果展示(The realization of the median filter function of the image, the file has the effect of display)