移位乘法器的输入为两个4位操作数a和b，启动乘法器由stb控制，clk信号提供系统定时。乘法器的结果为8位信号result,乘法结束后置信号done为1....

altera niosii SOPC helloword 学习-altera niosii SOPC helloword learning

花了半个月才改好的Atera DE1/DE2 ps2 IP 驱动核。放在FPGA工程目录下可以直接使用。本IP能够驱动PS/2键盘和鼠标。使用时只要调用HAL目录下的文件即可以直接使用！-Spent a good two weeks we have made some changes Atera DE1/DE2 ps2 IP-driven nuclear. On the FPGA project directory can be used directly. The IP to drive PS/2 keyboard and mouse. When used as long as the call HAL directory file that can be used directly!

FPGA开发超声波测距，可改写工业探伤或倒车测距等系统，quartus2下选择EP2C5Q208C8（CycloneⅡ） 支持目前淘宝上能买到的所有4-5针超声波模块 应用cycloneⅡ自带除法模块 开发板为有光技术YG2.1 生成电路规模较小 ！！注意：移植程序仅需重新约束数码管和超声波模块的针脚 (Ultrasonic Ranging FPGA development, industrial inspection or reverse rewritable ranging systems, EP2C5Q208C8 (CycloneⅡ) under quartus2 4-5 needle ultrasonic module supports all currently scouring the treasure can buy Applications cycloneⅡ own division module Development board bright technical YG2.1 Small scale generating circuit ! ! Note: The migration program only re-constraint digital and ultrasonic modules Pin)

说明：  使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。(The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.)

图像采集、存储控制verilog源代码，fpga控制SAA1117,采集数据存储到sram，仿真编译测试都能通过(Image acquisition, storage, control verilog source code, fpga control SAA1117, collecting data to sram, simulation tests can be compiled by)

FPGA通过AXI总线传输数据给ARM,ARM使用DMA方式接收数据！(FPGA to ARM Bridge design example)

一个简单的用verilog实现的售货机状态机设计，内有word介绍设计的原理(A simple realization of a vending machine with verilog state machine design, there are design principles introduced word)

基于 verilog的卷积运算代码，应用于离散小波分析。(verilog conv)

基于FPGA的1024点流水线工作方式的FFT实现,适合fpga的技术人员做信号处理参考-FPGA based on the work of the 1024-point pipelined FFT approach the realization of the technical staff for doing fpga signal processing reference

Xilinx FPGA reset usage