Features: Based on the VHDL language, realize high

lgpl RS编解码 5-6 Reed-Solomon Codes-LGPL RS codec 5-6 Reed-Solomon Codes

these files are written in verilog but i am uploading in text format

该计数器可以实现从0到1000的技术，程序简练执行效率高(counter1000)

乘法器功能 直接实现两个数字信号的相乘～-Multiplier features two digital signal direct implementation of the multiplication ~

用FPGA实现sos摩尔密码，即输出电平信号短长短。就是有次序的控制输出莫斯密码的“点”，“画”和“间隔”。而 control_module.v 是一个简单的定时触发器，每一段时间都会使能sos_module.v。(Realized by FPGA sos mole password, the output signal level of short duration. There is a sequence of output control points Moss password, painting and intervals. And control_module.v is a simple timer triggers, each period of time will enable sos_module.v.)

xilinx 平台的SPI从接口实现源码，供参考学习(used xilinx,slave-spi interface.)

I2C控制核设计,由VHDL语言编写,使普通I/O端口实现I2C性能-I2C control of nuclear design, VHDL language, I/O ports I2C Performance

BCD to 7 segments display decoder

用FPGA实现DDS的原理图，结构清晰，采用总线方式与外部单片机通信-FPGA realization of DDS with the schematic diagram, structural clarity, the use of bus-way communication with the outside Singlechip

这时manchesite编码，VERILOG语言，VHDL的找本站我发的帖子-manchesite time coding, VERILOG language, VHDL I find a site in a posting