I2C slave 代码，可以完成从机功能

这个代码可以用来分裂振荡器的频率和产生 1 赫兹信号从 100 兆赫的 vhdl 语言使用的 Nexys 3 板。 这可以用作闹钟或数字时钟中的组件数秒。

Xilinx 公司Spartan-6系列FPGA实现LVDS，带Modelsim仿真文件，已综合。(Xilinx Spartan-6 Series FPGA implements LVDS with Modelsim simulation file, which has been synthesized.)

A Dec example written in VHDL.

用VHDL编写的串口通讯程序，包括几个不同的程序例子，也可以用verilog进行改写。()

fifo的代码,经过测试可以使用，很有用处，可以放心使用(a fifo module,the code has been tested and it is usefull)

this is code verilog

本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)

RS（255，223）编码器，已实际运用到产品中(RS (255,223) encoder has actually applied to products)

电梯控制，包括楼层按键相应，显示上下状态。(Elevator control, including the floors of the corresponding button to show the whole state.)

说明：  (Springer Series in Advanced Microelectronics 51) Ayan Palchaudhuri, Rajat Subhra Chakraborty (auth.)-High Performance Integer Arithmetic Circuit Design on FPGA_ Architecture, Implementation and Desig