CH4CH2CH1VHDL 数字电路参考书所有程序5

led 点阵显示led――rom实现，功能模块分离 就爱可根据卡加大公开吉安市贷款给经济 -led dot matrix display led-- rom realized, functional modules can be separated on the basis love Cagayan open to the public Ji"an City loans to the economy

一个双向总线的vhdl实现-a two-way bus VHDL achieve

I2C端口的FPGA实现，网上较多，但发现不少有问题，这个是在网上代码的基础上修改过，验证可行。-I2C port FPGA, online more, but found that many problems This is a code on the Internet on the basis of the revised test feasible.

design cpu 16 bits by verilog HDL.

浙江大学体系结构实验课代码 实现5级流水线带有停顿，旁路和控制竞争的处理。(Experimental Architecture, Zhejiang University course code with a pause 5-stage pipeline, bypassing the treatment and control of competition.)

这是基数 4 修改 Booth 型乘法器为 8 位。它可以用于任何大小的操作数的乘法......

这是一个计算器的Verilog代码，可实现加减乘除等基础功能(calcultor for you to do some reserches.)

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像增强处理,平滑,锐化,滤波(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image enhancement, smoothing, sharpening, filtering)

图像采集 VGA输出 图像的边缘 ov7670(V image acquisition VGA output image edge)

说明：  lattice的官方8b10b代码, 1012年版本，diamond3.5编译。(lattice 8b10b encoder decoder code)