CH4CH2CH1VHDL 数字电路参考书所有程序5

Counter written in VHDL.

使用verilog硬件设计语言在FPGA板子上STOPWATCH 秒表设计。(Using verilog hardware design language STOPWATCH stopwatch design on FPGA board.)

在quartusII环境下采用对编解码芯片HD6408和HD6409驱动的方式实现曼彻斯特编解码(Environment in quartusII codec chip used on the HD6408 and HD6409-driven way to achieve encoding and decoding of Manchester)

说明：  serdes中的8B/10B编码 verilog实现(Implementation of 8B / 10B coding Verilog)

利用FPGA来采集美新加速度计的数据，并将FPGA采集到的数据传给ARM系统处理-The use of FPGA to collect the new U.S. accelerometer data and the data collected FPGA passed ARM system processing

通过神经网络实现的PID算法，整个工程文件，调试通过。(By PID algorithm neural networks, the entire project files, debugging through.)

初学学习verilog的经验，可以帮助新手以正确的思维方式，学习方法学习。(Verilog learning experience)

此程序是Verilog HDL语言读写RAM的程序希望大家有用(This is Verilog HDL Promang)

ofdm系统的matlab实现，包括插入导频信号和循环前缀(Matlab implementation of ofdm system, including inserted pilot frequency signal and the cyclic prefix)

用于FPGA的反Z变换算法的Verilog代码。可用于JPEG及MPEG压缩算法。-FPGA for the anti-Z transform algorithm of Verilog code. Can be used in JPEG and MPEG compression algorithms.