FPGA基于VHDL的Turbo码

本verilog代码通过IIC总线实现了对 PCF8591AD、DA转换芯片的控制。适用于FPGA，亲测可用。(this is used for FPGA to control PCF8591(AD/DA) chip by verilog.)

ip core of the transceiver gtx

此为多功能数字电子钟的vhdl代码，有闹钟、时间可调、计时等功能-This is a multi-function digital electronic clock VHDL code, has an alarm clock, time adjustable, timing and other functions

使用IEEE.STD_LOGIC_1164.ALL; - 取消对以下库声明，如果用符号或无符号值using--算术功能 - 使用IEEE.NUMERIC_STD.ALL; - 取消对以下库声明如果instantiating--任何Xilinx基元在这代码.--库UNISIM; - 使用UNISIM.VComponents.all;实体看门狗端口（SYSRST：在STD_LOGIC; SYSCLK：在STD_LOGIC; WR：在STD_LOGIC; DATAIN：在STD_LOGIC_VECTOR（7 DOWNTO0）; RESETOUT：出STD_LOGIC; debugStates：出STD_LOGIC_VECTOR（1 DOWNTO0）; debugDivider：出STD_LOGIC; debugFlag：出STD_LOGIC）;年底看门狗，看门狗建筑行为issignal timeoutSelect：STD_LOGIC_VECTOR（1 DOWNTO0）;信号timerRestart：STD_LOGIC;信号timerEnable：STD_LOGIC;组件wdtcntl端口（调试：出STD_LOGIC_VECTOR（1 DOWNTO0）;系统时钟：在STD_LOGIC; SYSRST：在STD_LOGIC; WR：在STD_LOGIC; DATAIN：在STD_LOGIC_VECTOR（7 DOWNTO0）;重新启动：从STD_LOGIC; timerEnb：出STD_LOGIC; timerSel：出STD_LOGIC_VECTOR（1 DOWNTO0））;最终组件;组件wdt_timer端口（dbDivider：出STD_LOGIC; DBFLAG：出STD_LOGIC; SYSRST：在STD_LOGIC; SYSCLK：在STD_LOGIC;启用：在STD_LOGIC;重启：在STD_LOGIC; RESETOUT：出STD_LOGIC; timeoutSel：在STD_LOGIC_VECTOR（1 DOWNTO0 ））;结束部分; begincontroller：wdtcntl端口映射（debugStates，系统时钟，SYSRST，WR，DATAIN，timerRestart，timer

FPGA实验，实现了蜂鸣器发出不同的音调，利用按键，很好玩的-FPGA experiment, realized the buzzer sounded a different tone, the use of keys, it is fun

实现千兆以太网数据发送，通过GMII接口向PHY写数据，控制PHY发送数据。(Implementation of Gigabit Ethernet data transmission, write data to the PHY through the GMII interface, control PHY data.)

本文研究的IIC总线控制器具有如下特征 1.兼容飞利浦I2C标准，以主机模式与外围设备进行数据通信，对IIC从机模型进行读/读，读/写，写/写，写/读[18]。 2.多主操作 3.软件可编程时钟频率 4.时钟拉伸和等待状态生成 5.软件可编程确认位 6.时钟同步设计 7.仲裁中断丢失，自动转移取消 8.开始/停止/重复启动检测/确认生成 9.总线忙检测(The IIC bus controller studied in this paper has the following characteristics. 1. Compatible with Philips I2C standard, data communication between host mode and peripheral devices, read/read, read/write, write/write, write/read for IIC slave model [18]. 2. Multiple Main Operations 3. Software programmable clock frequency 4. Clock stretching and waiting state generation 5. Software Programmable Confirmation Bit 6. Clock Synchronization Design 7. Loss of arbitration interruption and cancellation of automatic transfer 8. Start/Stop/Repeat Start Detection/Verification Generation 9. Bus busy detection)

the basic system of nexys3(soft core)

this is a simulation fm in simulink mathlab this is one program with pll

说明：  在quartus上运行16QAM仿真，实现在modelsim上的波形仿真(Running 16QAM simulation on quartus)