多功能信号发生器

quartusii 三分频电路，大家帮参考一下，有什么问题-one-third of quartusii frequency circuit, refer to U.S. help, have any problem

Vhdl实现计算exp功能 在apex20k上经过验证-Vhdl achieve in terms exp function on proven apex20k

在开发板EGO1上实现赛车游戏,语言为verilog，内含bits文件(racing game in verilog)

4通道12位AD芯片 AD7862控制模块,VHDL源代码,适于单次转换采样,250K采样率.-4-channel 12-bit AD chip AD7862 control module, VHDL source code, suitable for single conversion sampling, 250K sampling rate.

利用VHDL语言实现8位到32位的双向数据转换-use VHDL 8-32 two-way data conversion

自己编写的同步和异步FIFO的verilog代码，验证过，有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.)

有用的数字钟设计文档，有秒表、闹钟等模块，希望对大家有用！(JUST LEARN FROM IT!!ENJOY!)

卷积码（2,1,4）编解码的FPGA实现(Convolution code (2,1,4) decoding the FPGA implementation)

说明：  该文件包含了实现单周期cpu的全部代码以及实验报告，包括仿真波形以及烧板过程(This file contains all the codes and experimental reports of realizing single cycle CPU, including simulation waveform and download process)

这是fpga按键消抖的源代码，在很多fpga按键实验中都可以用到，能够进行代码移植。(This is the source code of the FPGA buttons, in many FPGA key experiments can be used, and can carry out code.)