多功能信号发生器

Description of a sistolic arhictecture for a FFT implementation in FPGA.

System Verilog for design verification

LCD显示超级玛丽游戏2 (LCD display Super Mario game)

  基于FPGA(Field-Programmable Gate Array)的OFDM(Orthogonal Frequency Division Multiplexing)信号传输系统VHDL源码 use IEEE.std_logic_unsigned.all; package outconverter is constant stage : natural := 3; constant FFTDELAY:integer:=13+2*STAGE; constant FACTORDELAY:integer:=6; constant OUTDELAY:integer:=9; function counter2addr( counter : std_logic_vector; mask1:std_logic_vector; mask2:std_logic_vector ) return std_logic_vector; function outcounter2addr(counter : std_logic_vector) return std_logic_vector; end outconverter; package body outconverter is function counter2addr( counter : std_logic_vector; mask1:std_logic_vector; mask2:std_logic_vector ) return std_logic_vector is variable result :std_logic_vector(counter"range); begin for n in mask1"range loop if mask1(n)="1" then result( 2*n+1 downto 2*n ):=counter( 1 downto 0 ); elsif mask2(n)="1" and n/=STAGE-1

FPGA实现DDS波形发生器，多种信号的产生，(FPGA realization of DDS waveform generator to produce a variety of signals,)

频移键控FSK的Verilog实现，带测试文件，并在FPGA开发板上成功验证(Frequency Shift Keying FSK the Verilog implementation, with the test file, and successfully verified in FPGA development board)

基于赛林思FPGA芯片， 控制采集芯片AD9226的程序(FPGA control AD9226 program)

实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 --A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 --各种波形的线形叠加输出。 (Achieve the four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency and amplitude controlled output (square wave- A duty cycle is controlled), can store arbitrary waveform feature data and can to reproduce the waveform, it can perform- all kinds of linear superposition of the output waveform.)

detection of the following sequence ‘10110110’in VHDL

FPGA编写环境，具有仿真容易，软件内存小的特点(FPGA authoring environment, with easy simulation software features small memory)