多功能信号发生器

用VHDL实现频率计，可测量输入脉冲的频率，并进行简单校正(Realize the frequency of use of VHDL in terms of measurable input pulse frequency, and a simple correction)

Verilog HDL语言编写的5分频电路。采用两路时钟相逻辑作用产生。-Verilog HDL prepared by the five-frequency circuits. Clock using two phase logic role.

C源碼16C550 串口驅動，使用中斷收送RS232資料(16C550 UART Driver)

基于FPGA的PCM编码器与解码器的设计-about fpga and pcm

VHDL的基本数学运算库,非常好用-VHDL basic arithmetic library, a very handy! !

说明：  生成一个M伪随机序列码，在ISE平台上可跑通(Generate an M Pseudo-Random Sequence Code which runs on ISE platform)

基于FPGA的相位测量原理图，通过对正弦信号过零比较进入FPGA，测量相位差。可用于测量导纳等应用中。

基于VHDL的SDH专用芯片的TOP-DOWN设计， 内有全套源码以及图片，内容详尽，绝对真实可靠！(VHDL based on the SDH ASIC Design TOP-DOWN, which has a full set of source code, as well as pictures, and detailed, reliable and absolutely true!)

用以VGA显示的小程序，很实用，挺有价值的(VGA display for a small program, very practical, quite valuable)

此示例是8051核加频率计的联合设计,带有8051IP核资料-This example is the 8051 nuclear increase the frequency of joint design, with the nuclear information 8051IP