实现dds功能，利用quartus软件， 子模块包括加法器，锁相环，date...

用NiosII实现的数字钟，经过本人测试运行正常，开发环境：QuartusII6.0和NiosII IDE6.0-NiosII achieved with digital clock, after I run the normal tests, development environment: QuartusII6.0 and NiosII IDE6.0

乐曲演奏电路，能演奏歌曲，同时在数码管上显示演奏的乐曲音符的数字。-Music concert circuit, can play songs at the same time in the digital tube displays the number of notes played music.

基于ISP的交通灯设计，实现了各路状态转换、警察控制、行人请求功能。(ISP traffic light design, to achieve the brightest state transitions, police control, pedestrian request feature.)

Clifford E. Cummings论文合集，其中关于FIFO的设计很经典(Clifford E. Cummings collection of papers, on the FIFO design classic)

user_logic_VGA_Controller，适合于DE2开发板，把这个文件夹放在工程目录之中，就可以在SOPC里直接添加VGA_Controller IP核了，很方便使用。-user_logic_VGA_Controller. suitable for Dictyophora development board, this folder on the project directory, it can be added directly SOPC Lane VGA_Controller IP core, very convenient to use.

uvm验证方法学入门。step by step，适合IC验证人员入门(uvm verification methodology started. step by step, for IC verification personnel entry)

主要通过频率分配 实现不同时间的变化 达到呼吸一闪一闪的效果

本实验教程选用Xilinx公司的产品X9572，与之配套的开发软件为ISE4.1i，可进行原理图的输入和VHDL硬件描述语言的输入，并且可利用Modelsim进行功能仿真和时序仿真。-In this study, selected Xilinx tutorial products X9572, with supporting the development of software for ISE4.1i, schematic can be input and VHDL hardware description language input, and can use Modelsim functional simulation and timing simulation.

FPGA verilog 实现任意位宽的移位相乘法，有符号小数或者有符号整数相乘。函数调用方式(FPGA verilog achieve any bit-wide shift multiplication , signed or signed decimal integer multiplication . Function call )

基于vhdl编写的贪吃蛇游戏，课程设计必备(Based on the VHDL language of the snake game, curriculum design essential)