实现dds功能，利用quartus软件， 子模块包括加法器，锁相环，date...

用FPGA中的三速以太网来实现UDP通信，功能强大(With a triple-speed Ethernet in the FPGA to implement UDP communication, powerful)

比较实用的ps2键盘源码 可以在SOPC中进行添加组件 以实现自己所需的功能-Comparison of practical ps2 keyboard source code can be carried out in the SOPC components add to the functionality required to realize their own

DESCRIPTION OF FULL ADDER

这是一个计算机组成原理综合性实验：设计8位cpu。该cpu是8bit的代码，包含有4个寄存器，一个存储器，还有alu以及控制器。一共可以实现16条指令。(This is a computer composition principle of comprehensive experiment: Design 8 cpu. The cpu is 8bit code contains four registers, a memory, as well as alu and controllers. A total of 16 instructions can be achieved.)

多年项目经验测试文档测试文档，重要保存重要保存重要保存重要保存重要保存重要保存(Years of project experience testing document testing, it is important to save save save important important important important to save save save important)

数字信号除了的FPGA实现的Verilog源代码，之前发过一份是VHDL，各有所需吧，需要的看看吧(Digital signal in addition to the realization of the FPGA Verilog source code, send before a is VHDL, each have need it, need to look at it )

说明：  此代码是由FPGA产生SPWM波的代码，简单易懂(use FPGA to generate SPWM)

PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF

用verilog hdl语言编写的fpga与片外sram 的读写控制(With the verilog hdl language fpga sram chip with read and write control)

detailed spec for Xilinx V5 FPGA, reference for programming of FPGA, system designer or ASIC designer.