使用VHDL高级Turbo解码器

实施256点，

fpga驱动TLC7528程序，相当好用，绝对能用(FPGA PROGRAM OF TLC7528)

TEXIO study testbench passed VHDL FPGA CPLD simulation Altera quartus

步进电机驱动，32等级速度，带加减速度控制。verilog编写。(step motor driver,32 level speed.)

VHDL同步串口发送部分，基于Xilinx ISE的编程平台(synchronous serial port sending part on VHDL)

bch编解码的完整版，本人已经做过fpga实现，就是按照该程序为原型，绝对可运行(bch decoding the full version, I have done fpga implementation is in accordance with the procedure for the prototype, can certainly run)

这个程序是 用于两个浮点数字加法器使用 VHDL 语言。

基于NIOS驱动ALTERA DE1开发板的GPS模块工程-based on the nios ii drive the gpa module of altera de1 develop board,it s only a reference project

一个简单的用verilog实现的售货机状态机设计，内有word介绍设计的原理(A simple realization of a vending machine with verilog state machine design, there are design principles introduced word)

Testbench 不仅要产生激励也就是输入，还要验证响应也就是输出。当然也可以只产生 激励，然后通过波形窗口通过人工的方法去验证波形，这种方法只能适用于小规模的设计(The Testbench not only to generate incentives to input, verify that the response is output. Of course, can only produce Incentive, and then the waveform by the waveform window by artificial means to verify, this method is only applicable to small-scale design)