verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，9...

自已写的一个16X16的乘法器，速度比较慢。初学者练习练习！-own writing an audio Multiplier, speed is relatively slow. Beginners practice practice!

16次迭代的CORDIC算法，精度很高，可应用于计算反正切值(16 iterations of the CORDIC algorithm, high accuracy, can be applied to calculate arctangent)

一个简易的数字频率计，可以对一个输入的信号频率进行测量并显示输出，适合VHDL的初学者-A simple digital frequency meter, you can enter the signal of a frequency measurement and display output, suitable for beginners VHDL

74ls161 基于verilog语言的实现 源程序在压缩包的hdl文件夹中(74ls161 language based on the realization of verilog source package in compressed folder hdl)

VHDL实用教程，详细介绍VHDL语法、开发环境、应用实例等。。。(VHDL course)

fifi asyncronous and syncronus

REEDSOLOMON source code

fpga VHDL语言，控制DDS产生频率可变的正弦波信号扫频-FPGA VHDL DDS

nseval - Object evaluation, includes control method execution.

本文件是用CPLD（EPM7064）驱动线阵CCD（ILX509），其中包括原理图和程序-This document is a CPLD (EPM7064) driver line array CCD (ILX509), including schematics and procedures