VHDL写的PWM发生器，仿真通过，波形基本完美，可以用于直流电机的控制...

VerilogHDL教程，很详细全面的Verilog教程，循序渐进，由浅入深，十分好的学习资料(VerilogHDL tutorial, very detailed and comprehensive Verilog tutorial, step by step, progressive approach, a very good learning materials)

fpga 设计全攻略，很好的fpga入门提高资料(the fpga design Raiders, good fpga the Getting Started improve data)

自动白平衡的verilog实现 通过逻辑实现了白平衡算法(awb design awb design awb design awb design awb design )

VHDL 源码模块，可以实现最经典原PWM，可以用于电源，电机的控制()

UART communication on SPARTAN 6 it contains tx and rx

signaltap 中文说明，内容详细。 ALTERA signaltap USER GUIDE IN CHINESE(ALTERA signaltap USER GUIDE IN CHINESE)

自适应滤波器算法LMS ，的FPGA实现，采用VERILOG实现。(LMS, an adaptive filter algorithm, is implemented on FPGA and VERILOG.)

4、各个功能的主要源程序 1、移相模块： = 1 * GB2 * MERGEFORMAT ⑴、相位累加器： architecture one of add32 is begin   s

crc校验,经验证正确,下载就可直接用,有不足的地方可以指正,-CRC check, certified correct, you can download directly, there are deficiencies can correct me,

VHDL_count 从 0 到 9 4 7 段 LED 显示器 (đếm 0 đến 9 hiển 施耐 4 带领 7 đoạn)