JOP kernel, which is the core of the core, the Chinese can not find basic inform...

本人编写的FPGA光电编码器输入模块,没有实验,但仿真基本实现,希望有参考价值.(FPGA optical encoder input module, there is no experimental, but simulation technology, hope to have reference value.)

增强型8051的VHDL源代码，两个周期执行一条指令，仿真工具为Modelsim，开发板为Altera的EP1C20开发板-enhanced 8051 VHDL source code, the implementation of a two-cycle instruction, simulation tools for Modelsim, development board for the Altera EP1C20 development board

VGA 测试程序，可显示彩色条纹，用vhdl语言编写，经过测试，运行稳定，带有注释！-VGA test procedure can be displayed color stripes, using VHDL language, tested and stable operation with Notes!

这是一个用vhdl编的多功能电子秒表，可以记录几个人的时间，并且可以在跑秒的时候查看记录。。〔原创〕-This is a series with VHDL multifunctional electronic stopwatch, can be recorded by several people, and that they could run in the second examined the records. . [Original]

this is code verilog

FPGA部分源代码，关于dsp48的应用，从一本很好的书上下的

this a spartan 3E base project file. this is the project of game in which vga is interfaced to FPGA. this file is main file in which vga timing is maintained.-this is a spartan 3E base project file. this is the project of game in which vga is interfaced to FPGA. this file is main file in which vga timing is maintained.

SDRAM_DDR控制器verilog代码及中文说明文档。(The SDRAM_DDR controller Verilog code and documentation in chinese.)

图像采集、存储控制verilog源代码，fpga控制SAA1117,采集数据存储到sram，仿真编译测试都能通过(Image acquisition, storage, control verilog source code, fpga control SAA1117, collecting data to sram, simulation tests can be compiled by)

说明：  是用VHDL语言编写的乐曲演奏程序，详细的写了各个模块的子程序(VHDL language is the music playing program)