VHDL example, there are nearly a hundred examples, can be carried out in quartur...

un controller pi par le langage VHDL xilinx ise design 13.2

logic lock 的vhdl源码，altera平台适用。-logic lock the VHDL source code, altera platform.

用VHDL和verilog编写的RGB颜色空间到YUV颜色空间的转换程序, 是FPGA视频处理中的常用程序!(Written in VHDL and verilog using RGB color space to YUV color space conversion process is commonly used in video processing FPGA program!)

中文版DLX流水线技术相关方面介绍以及简单应用 适用于面对初学者讲解(Chinese version of the DLX pipeline technology-related aspects of introduction and a simple application Suitable for beginners to explain face)

说明：  fpga程序，产生1pps脉冲信号，使用的verilog语言。(FPGA program generates 1 PPS pulse signal, using Verilog language.)

EAB_VHDL

通过串口发送，实现FPGA与stm32的dds发生器(Implementation of DDS generator)

LATTICE FPGA FIFO 程序例程，工程详细，全部源代码上传 (LATTICE FPGA FIFO routine, detailed engineering, all source code uploaded)

实现4倍抽取的CIC抽取滤波器模块的Verilog实现，在对数据进行抽取之前，首先进行滤波(Extracted 4 times realize CIC decimation filter module Verilog realize that in the data collected before the first filter)

用VHDL实现十六位移位乘法器 才有移位相加法来实现-Use VHDL to achieve 16-bit shift multiplier shift only the sum of law to achieve