VHDL example, there are nearly a hundred examples, can be carried out in quartur...

本章介绍了两个EDA技术的综合应用设计实例:数字闹钟和直接数字频率合成器DDS。-EDA chapter describes the two technologies integrated application design example: digital alarm clock and direct digital synthesizer DDS.

KDP晶体二倍频与三倍频；基于耦合波方程组；已于实验结果校核 (Sum Frequency in KDP)

verilog 写的 多功能数字钟-verilog to write multi-functional digital clock

说明：  一个简单的千兆以太网UDP协议的实现,可以实现数据的收发和ARP，实现PC端与FPGA的以太网通信(A simple implementation of Gigabit Ethernet UDP protocol can realize data sending and receiving and ARP, and realize Ethernet communication between PC and FPGA.)

全部通过，是我的精心设计，完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.

verilog编写的并行256点fft代码(Verilog prepared parallel 256 points fft code)

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uart implementation and documentation, this describes the basic steps in building your own uart module on verilog and programming them on an fpga device

一个简单移位寄存器代码，verilog HDL编写(a simple shift register example，write with verilog HDL)

Quartus中实现的DDS 使用的是altera提供的IP core-DDS achieved Quartus using IP core provided by altera