基于FPGA的门级逻辑实现快速乘法运算的verilog源程序。

贪吃蛇程序，用verilog实现，可以运行只要修改一下相应的FPGA芯片类型和VGA接口相应的引脚(Snake program, using Verilog to achieve, you can run as long as the appropriate to modify the corresponding FPGA chip type and VGA interface to the corresponding pin)

通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.

用Verilog语言编写的产生正弦波和方波的程序(Generate sine and square wave Verilog language program)

用verilog写的基于cpld的出租车计费器的源码，需要的参考一下-Use verilog to write a taxi based cpld billing device source code, need to refer to

GAL16V8(仿真74LS138),试验通过。包括able及jed文件。对pcb印板设计时，对简化走线特别有用。简单的修改GAL16V8程序，可灵活地进行地址译码修改。(GAL16V8 (simulation 74LS138), test passed. Including the able and jed file. Printed on the pcb board design, especially useful to simplify alignment. Simple modifications GAL16V8 program, the flexibility to change the address decoding.)

使用VHDL语言实现了FPGA与DAC5688进行SPI通信更改寄存器值(The FPGA using VHDL language with the DAC5688 SPI communication to change the register value)

说明：  假设每个从设备中有可访问APB寄存器16个，位宽均为32比特，16个寄存器的访问地址计算方式为 基址 +　寄存器编号左移２位（byte 偏移）(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)

说明：  verilog语言编写的简单FPGA 的从机模式 spi 通讯(Slave mode SPI communication of FPGA)

串行加法器的vhdl描述，用两个移位寄存器和一个全加器，一个d触发器实现(The VHDL description of the serial adder, with two shift registers and a full adder, a D trigger)

本文首先对多功能车辆总线的基本原理进行了简要的概述，接着对其实时协议进行了分析，然后对 MVB2 类设备控制器的功能及其功能模块的划分设计进行了详细的分析；最后对各功能模块进行了编程实现，并给出了仿真验证波形。(Firstly, the basic principle of the multifunction vehicle bus are briefly outlined, then analyze the real time protocol, then carried out a detailed analysis of the classification of the design function and the function module of the MVB2 device controller; finally, the function of each module of the program, and gives the simulation waveforms.)