四位抢答器

vhdl,序列信号检测模块，此模块检测1110010，可改为任意序列，输出电位为1为检测出，否则为0-vhdl, sequence of signal detection module, this module testing 1.11001 million, can be changed to an arbitrary sequence, the output potential of an as detected, otherwise 0

在赛灵思的FPGA上实现turbo码的编码程序,使用Verilog语言实现。(Implemented on Xilinx FPGA in the turbo coding principle, the use of Verilog language.)

vhdl source code for 8 bit datapath logic

binary adder / subtracter in vhdl

说明：  关于地铁售票的一些功能 基于自动买票的VHDL设计程序 比较经典(Subway ticket on some of the features of the VHDL-based auto-buying classic design procedure)

sigmoid函数硬件实现，verilog代码及其测试用例(Sigmoid function hardware implementation, verilog code and test cases)

lap trinh FSM may trang thai

vhdl code for decoder and detemines the basic mechanism of gates of decoder

VHDL code for converting BCD to Decimal

个人搜集的各类Modelsim教程全集视频PDFWordPPT等.rar(Personal collection of all kinds of Modelsim tutorial video PDFWordPPT Complete Works, etc.. Rar)