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1
说明: 单周期cpu,使用verilog编写的的单周期cpu支持......等功能(Single cycle CPU, using Verilog written single cycle CPU support... And other functions)
- 2021-03-15 08:45:07下载
- 积分:1
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波形发生器,用于编写testbentch文件。非常实用
波形发生器,用于编写testbentch文件。非常实用-Waveform generator, for the preparation of testbentch files. Useful
- 2022-10-22 19:55:04下载
- 积分:1
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Multisim
multisim 程序
使用教程 详细明了清楚(multisim tutorial program uses more clearly understand)
- 2010-09-15 22:56:42下载
- 积分:1
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Dec_mul
时间同步后即可确定每帧数据的起始位置,这样就能完整的截取下每一帧。但是,数据中还带有频偏信息。在常规的通信系统中,多普勒很小仅仅会带来很小的频偏,但是在大多普勒的情况下,频偏将非常大,20马赫的速度将会带来将近34K的频偏。因此,如何很好的纠正频偏即为本系统的难点。
OFDM中,我们将大于子载波间隔倍数的频偏称为整数倍频偏,而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔,频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想,由于硬件资源限制,我们将在接收端做64点FFT,即相当于将频域划分为64份,我们将小于 的频偏称为小数倍频偏,将 整数倍的频偏称为整数倍频偏。本程序即基于SCHIMDL经典方法完成小数倍频偏纠正(After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication systems, doppler small will bring only small deviation, but in the case of most of the doppler, frequency PianJiang is very large, 20 Mach speed will lead to deviation of nearly 34 k. Therefore, how to good to correct deviation is the difficulty of this system.
OFDM, we will be bigger than the sub-carrier spacing ratio of frequency deviation is called the integer frequency offset, and the interval will be less than a child carrier frequency offset is called decimal frequency doubling. Deviation is less than one over ten times as long as can guarantee accuracy of sub-carrier spacing, deviation will not affect balance and demodulation. This article, we draw lessons from the idea, due to the limited hardware resources, we will do 64 points FFT at the receiving end, which is equ)
- 2013-12-26 18:00:24下载
- 积分:1
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RS485
verilog开发FPGA,实现RS485串口通信(RS485 driver for FPGA )
- 2021-02-08 06:49:54下载
- 积分:1
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z80_latest.tar
Vhdl design z80 for altera users
- 2013-04-24 14:47:01下载
- 积分:1
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数字逻辑课程设计,用vhdl实现红外线传输系统的课程设计,下载验证通过...
数字逻辑课程设计,用vhdl实现红外线传输系统的课程设计,下载验证通过-Digital logic course design, using vhdl infrared transmission system to achieve curriculum design, download verified by
- 2023-07-10 17:40:03下载
- 积分:1
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mips3
Modelsim+DC开发的4级流水线结构的MIPS CPU(mips 4level cpu)
- 2020-08-08 11:18:30下载
- 积分:1
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verilog例子资源,对于初学者很有帮助。
verilog例子资源,对于初学者很有帮助。-verilog examples of resources are very useful for beginners.
- 2023-08-15 15:30:03下载
- 积分:1
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comp
The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.
- 2012-06-05 23:16:25下载
- 积分:1