是使用VHDL语言编写的基于FPGA的uart的源代码！

四位动态刷新数码管显示，ＶＥＲＩＬＯＧ代码，含详细的中文注释．-Four dynamic refresh digital tube display, VERILOG code, with detailed notes in Chinese.

vhdl参考程序，供初学者参考使用-VHDL reference procedures, their use and reference for beginners

内附多路选择器，74系列芯片VHDL源码，加法器，FIR，比较器等大量例子，对初学VHDL语言很有好处。可用maxplus，quartus，synplicity等综合软件进行调试-contains multiple-choice, 74 chips VHDL source code, the adder, FIR, comparators, etc. are plenty of examples for beginners VHDL very good. Available maxplus, Quartus, synplicity integrated software debugging

FCFS (First Come First Served) with Database

介绍专用集成电路设计的一本书，很有参考价值，适合高年级本科生和研究生(Introduction ASIC design a book, a good reference for senior undergraduate and postgraduate)

使用vhdl语言实现对led的控制，还有电路仿真-Using vhdl language implementation of the led control, as well as circuit simulation

说明：  利用正点院子开拓者fpga实现DDS功能，实现三角波、正弦波、方波的发生。(Implementation of DDS with FPGA)

高速双端口RAM的vhdl实现。包含仿真波形-High-speed dual-port RAM realize the VHDL. Contains the simulation waveform

Altium Reference design for LMH0340 test bed and design

这些代码为 对于基本的FPGA使用模块beep进行了例化 在工程 系统级建模时只需要直接调用就好了(The code for the basic FPGA using the module beep instantiated only need to be called directly in the engineering system-level modeling like)