是使用VHDL语言编写的基于FPGA的uart的源代码！

温度控制系统.运用ds18b20温度传感器将实时温度送入FPGA中，再将温度显示出来(Temperature control systems. Use ds18b20 temperature sensor into the FPGA in real-time temperature, then the temperature is displayed)

该程序实现的N位全减器，首先实现一位的减法器，之后实现N位全减器。-Program of the N-bit-wide reduction, the first realization of a subtraction for, after all N-reduction devices.

Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download

说明：  USB主机和设备的verilog代码，实现了USB1.1协议规范的要求(USB host and equipment Verilog code to achieve the USB 1.1 protocol specification requirements)

一些对初学者比较实用的源码，ASK，PSK，FSK调制解调(Some of the more practical source code for beginners)

自己编写的AD7667的数据采集程序，因为之前没用过，首次写！

结合XILINXCPLD所做的模拟RS232通信verilog源程序-XILINXCPLD combine the simulation RS232 communication Verilog source

Sample behavioral waveforms for design file sin_rom.vThe following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design sin_rom.v. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 3F0, 3F1, 3F2, 3F3, ...). The design sin_rom.v has one read port. The read port has 1024 words of 10 bits each. The output of the read port is unregistered. Fig. 1 : Wave showing read operation. The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until

数字逻辑与系统的关于所有的器件74LS的介绍，功能表(Digital Logic and System devices 74LS on the introduction of all the menu)