数字时中（VHDL）

VHDL数字系统设计工程实践，包含实验的原理，真值表和结构图描述，以及相关的VHDL代码。-VHDL digital system design engineering practice, including the principle of the experiment, truth table and chart descriptions, and associated VHDL code.

基于verilog的DDS设计,内附代码,仿真环境等说明(the DDS design based on verilog)

表决器，简单实现了表决功能，无显示功能 -vote

verilog实现的“状态机实现AD574数模转换”-verilog to achieve a " state machine to achieve AD574 digital-analog conversion"

How to Connecting Xilinx FPGAs to the Philips

本实验实现了一个小的乒乓游戏，VGA显示,代码下载的FPGA板子上验证通过，效果很好。(The experimental realization of a small ping-pong game, VGA display, download the code verified by the FPGA board, with good results.)

Two-Dimensional Rank Order Filter Author: Gabor Szedo

ICA (Principal Component Analysis) algorithm and procedures, GSM is GMSK modulation signal generation, On neural network control.

多功能波形发生器VHDL程序与仿真 URAT VHDL程序与仿真 ASK调制与解调VHDL程序及仿真 LCD控制VHDL程序与仿真-Multi-function waveform generator and simulation of VHDL procedures URAT VHDL simulation procedures and ASK modulation and demodulation procedures and VHDL simulation program LCD control and simulation of VHDL

本例是关于卷积码的一个简单算法，用verilog HDL语言编写，整个文档包括了产生卷积的整个工程。-In this case is a convolutional code on a simple algorithm, using verilog HDL language, the entire document, including the method of deconvolution of the whole project.