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shift example
shift example for verilog
- 2018-12-18 05:24:04下载
- 积分:1
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VHDL版的C51核(MC8051)
VHDL版的C51核(MC8051)-VHDL version of the C51 core (MC8051)
- 2022-06-19 21:32:45下载
- 积分:1
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rs-codec-8-16
RS[255,223]纠错码verilog源码,包含编码和解码模块,以及testbench等。(Verilog source code for RS[255,223] encoder and decoder, with testbench included.)
- 2021-04-28 15:58:44下载
- 积分:1
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在nexys2数字cronometer
该项目是用VHDL编写的,并在Nexys2板套件的4个七段显示器中显示一个测微计的秒、分和小时。时间可以在开关0中停止,在按钮0中复位。显示方式与显示方式不同最小:分段到hr:min通过切换开关1
- 2022-11-12 07:55:03下载
- 积分:1
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Altera_Audio
针对Altera的DE2/ DE1交互板的音频核心的音频编解码器(编码器/解码器),并提供了音频输入和输出的接口。(The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1
Boards and provides an interface for audio input and output.)
- 2015-04-01 22:21:49下载
- 积分:1
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LED
一个走马灯的程序,可以按照要求一个一个往后面按顺序点亮(A program for the lantern can be lit one by one according to the requirements.)
- 2019-06-28 15:18:09下载
- 积分:1
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master_slave
说明: AXI4-Lite总线的主从机读写,例程及代码(AXI4-Lite Bus Host-Slave Read-Write, Routine and Code)
- 2019-03-22 22:24:20下载
- 积分:1
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arbiter_ip
Arbiter code for simulation purpose
- 2013-07-13 17:45:11下载
- 积分:1
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UDP
用verilog实现的UDP协议,包括arp,udp,ip分段协议等,对于想用FPGA实现TCP/IP协议的人来说,应该会起到一定的帮助作用(Implemented with verilog UDP protocols, including arp, udp, ip fragmentation protocol, etc., who want to achieve TCP/IP protocol with the FPGA people, should play a helpful role)
- 2021-04-05 04:39:03下载
- 积分:1
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cnv_enc_modify
卷积码(2,1,7)编码器,一个输入,两个输出(Convolution code (2,1,7) encoder, an input and two outputs)
- 2015-05-20 10:21:56下载
- 积分:1