数字时中（VHDL）

基于FPGA的相位测量原理图，通过对正弦信号过零比较进入FPGA，测量相位差。可用于测量导纳等应用中。

this come from alter ,you can look and find it on line about jtag.

基于FPGA设计的电子密码锁是一个小型的数字系统，与普通机械锁相比，具有许多独特的优点：保密性好，防盗性强，可以不用钥匙，记住密码即可开锁等。(FPGA-based design of the electronic code lock is a small digital system. It has many unique advantages：good privacy and security , it do not need the key but remember password to unlock, and so on while it compare to ordinary mechanical locks.)

用Verilog HDL，实现的FPGA串口调试程序，已经在硬件上调试成功(With Verilog HDL, FPGA serial debugger implemented in hardware debugging has been successful)

vhdl编程语言电子书，英文的，有很多例子(VHDL programming language e-books, in English, there are many examples of)

a code to display in VGA using VHDL lang

结合XILINXCPLD所做的模拟RS232通信verilog源程序-XILINXCPLD combine the simulation RS232 communication Verilog source

usb1.1的设备控制器IP核，是用verilog硬件描述语言写的-USB1.1 IP core for device control, written with hardware describing language of Verilog.

8位加减器，八位减法器与加法器，用过一个控制端可以自由变换，采用移位加法方式，用途广泛，利用减法位补码加法的理论实现。(8 addition and subtraction, eight subtractor and adder, used a control terminal can freely change the using Shift addition, a wide range of uses, the use of subtraction complement addition theory to achieve.)