数字时中（VHDL）

LVDS的应用的Verilog HDL例子程序(LVDS example of the application procedures for the Verilog HDL)

用blockram实现移位寄存器，开发语言为verilog hdl(Shift register with blockram achieve the development language for the verilog hdl)

在Quartus中，利用FPGA例化的存储器实现程序的BOOTLOADER的搬移(In Quartus, the use of FPGA case of memory to achieve the program' s move BOOTLOADER)

SAA7113 ＦＰＧＡ开发实例，非常经典(The SAA7113 FPGA development examples, very classic)

EDA技术与VHDL课件，利用EDA技术进行电子系统设计(EDA technology and VHDL courseware, the use of EDA technology for electronic system design)

UC1608 24064驱动 COG LCD驱动程序(UC1608 24064)

数字时钟的VHDL语言描述，具有高精度，控制性能良好-Digital Clock description of the VHDL language, with high precision and good control performance

Actel FPGA A3P600最小系统原理图，包含JTAG 、电源和封装 (Actel FPGA A3P600 minimum system schematics, including JTAG, power and packaging)

1）选择一个语音信号作为分析对象，或录制一段语音信号； 2）对语音信号进行采样，画出采样前后语音信号的时域波形和频谱图； 3）利用MATLAB中的随机函数产生噪声加入到语音信号中，使语音信号被污染，然后进行频谱分析； 4）设计用于处理该语音信号的数字滤波器，给出滤波器的性能指标，画出滤波器的频率响应； 5）对被噪声污染的语音信号进行滤波，画出滤波前后信号的时域波形和频谱，并对滤波前后的信号进行比较和分析； 6）回放各步骤的语音信号，给出相应处理程序及运行结果分析。(1) Select a voice signal as an analysis object, or record a voice signal 2) sampling the voice signal, draw the waveform and frequency spectrum of the time domain before and after sampling the speech signal 3) using the random function in MATLAB generated noise was added to the speech signal, the speech signal to be contaminated, and then spectrum analysis 4) for processing the speech signal, the digital filter design, given the performance of the filter to draw the filter' s frequency response 5) on the noise pollution of the speech signal is filtered, time-domain waveform and spectrum draw before and after filtering the signal before and after filtering, and the signal for comparison and analysis 6) playback of the speech signal for each step, given the results of the corresponding processing procedures and run analysis.)