数字时中（VHDL）

用状态机实现密码锁State machine used to achieve code lock-State machine used to achieve code lock

具有16个校验位的RS编码器，在FPGA上实现。(With 16 RS encoder, the parity bit in the FPGA.)

本文件夹包含了16个VHDL 编程实例，仅供读者编程时学习参考。 一、四位可预置75MHz -BCD码（加减）计数显示器（ADD-SUB）。 二、指示灯循环显示器（LED-CIRCLE) 三、七人表决器vote7 四、格雷码变换器graytobin 五、1位BCD码加法器bcdadder 六、四位全加器adder4 七、英语字母显示电路 alpher 八、74LS160计数器74ls160 九、可变步长加减计数器 multicoun

卷积码(2,1,7)编码器，一个输入，两个输出(Convolution code (2,1,7) encoder, an input and two outputs)

交通灯通过数码管显示，几种模式可调，还可以时间可设，适合初学者入门参考学习。(LED traffic lights can be set to several modes adjustable time beginners reference ~ ~ ~)

脉动乘法器：一个GF(2m)域上的Digit-Serial 脉动结构（Systolic）的乘法器(Pulse Multiplier: a GF (2m) domain on the Digit-Serial pulsation structure (Systolic) the multiplier)

基于FPGA的AD和DA设计代码及文档(Design code and document of AD and DA based on FPGA)

里面包含了三段代码，主要是用matlab产生高斯随机信号以及高斯白噪声和色噪声，然后计算其数字特征及对这些信号进行频谱分析和功率谱分析，里面还有关于低通滤波器的设计的简单说明(Which contains three sections of code using matlab Gaussian random signals and white Gaussian noise and color noise, and then to calculate the numerical characteristics and spectral analysis and power spectral analysis of these signals, there is also the low-pass filter design BRIEF DESCRIPTION OF)

说明：  高清电子书4本合集-Verilog HDL数字系统设计教程4本合集(Digital circuit design Verilog HDL digital system design)

CODE_VHDL_COUNTING 0 到 9，使用按钮 (Đếm 慈 0 đến 9 hiển 施耐 1 带领 7 đoạn sử dụng nút nhấn để điều khiển) Với bài này tôi sử dụng một nút nhất để một nút nhấn đế bắt đầu đếm dữ liệu 将重置。