登录
首页 » VHDL » 数字时中(VHDL)

数字时中(VHDL)

于 2022-03-14 发布 文件大小:382.47 kB
0 141
下载积分: 2 下载次数: 1

代码说明:

数字时中(VHDL)-Numbers in (VHDL)! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 布斯算法结构的 VHDL 代码
    布斯算法用于在计算机体系结构的两个二进制现在的乘法。随着处理器为转移的运行情况良好,不能轻易做乘法这就是为什么正在使用它。
    2022-08-08 00:31:29下载
    积分:1
  • 7 digital display decoder design 7 Digital is pure combinational circuits, usual...
    7段数码显示译码器设计7段数码是纯组合电路,通常的小规模专用IC,如74或4000系列的器件只能作十进制BCD码译码,然而数字系统中的数据处理和运算都是二进制的,所以输出表达都是十六进制的,为了满足十六进制数的译码显示,最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器,输出信号LED7S的7位分别接数码管的7个段,高位在左,低位在右。例如当LED7S输出为“1101101”时,数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1;接有高电平的段发亮,于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as
    2022-08-11 21:55:01下载
    积分:1
  • DDC
    说明:  数字下变频verilog实现,项目中常用模块(apply the digital down frequency in my project)
    2020-12-08 11:29:20下载
    积分:1
  • With VHDL Design and Implementation of the multi
    用vhdl设计实现的多功能电子钟,可有日历,闹钟,修改等多种功能-With VHDL Design and Implementation of the multi-functional electronic bell, can have a calendar, alarm clock, to amend a variety of functions such as
    2022-03-11 03:55:41下载
    积分:1
  • encode
    RS(255,223)编码器,已实际运用到产品中(RS (255,223) encoder has actually applied to products)
    2021-05-13 00:30:02下载
    积分:1
  • jiaotongdeng
    数字电路课程设计,用VHDL实现交通灯的控制(Digital circuit design using VHDL control of traffic lights)
    2014-06-16 18:26:53下载
    积分:1
  • DW_apb_timer
    verilog实现计时器timer,可直接用于芯片开发中。(verilog achieve timer, it can be directly used for chip development.)
    2016-04-05 22:37:39下载
    积分:1
  • 本源码为Nios II的开发示例,主要演示Nios II的I2C总线设计。开发环境QuartusII。 本示例十分经典,对基于SOPC开发的FPGA初学者有...
    本源码为Nios II的开发示例,主要演示Nios II的I2C总线设计。开发环境QuartusII。 本示例十分经典,对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II I2C-bus design. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.
    2022-05-20 17:06:23下载
    积分:1
  • 04_uart_test
    说明:  基于FPGA的串口发送和接收,使用的verlilog语言(Using Verilog serial port program, send and receive.)
    2020-10-13 10:33:10下载
    积分:1
  • 用VHDL语言来实现一个电子时钟,可以调时间。小时,分,秒。可以下载到实验箱来运行验证。...
    用VHDL语言来实现一个电子时钟,可以调时间。小时,分,秒。可以下载到实验箱来运行验证。-use VHDL to achieve an electronic clock, the time can be set aside. Hours, minutes and seconds. Experiments can be downloaded to the box to run test.
    2022-07-21 04:12:49下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载