基于VHDL的自动售货机实现,包含完整的源代码,锁脚文件以及下载文件

8位相 加乘法器，具有高速，占用资源较少的优点-eight multiplier phase together with high-speed, taking up less resources advantages

本设计是一个伪随机数发生器。此设计；

使用Verilog编写的ad9826的控制模块(the module of ad9826 with verilog)

浙江大学体系结构实验课代码 实现5级流水线带有停顿，旁路和控制竞争的处理。(Experimental Architecture, Zhejiang University course code with a pause 5-stage pipeline, bypassing the treatment and control of competition.)

数字时钟的VHDL语言描述，具有高精度，控制性能良好-Digital Clock description of the VHDL language, with high precision and good control performance

R S编 解 码 实 现 代 码 verilog语言(RS CODE AND ENCODE)

说明：  verilog开发的经典教材，详细介绍了语法，常见历程，以及通用的程序段(verilog development of the classic materials, detailed information on syntax, common history, as well as the common program segment)

数字秒表的实现，我还写个具体的过程要求等，(there is function of clock,it very useful)

简易数字存储示波器verilog源代码 经过EP2C8Q208C8验证(Simple digital storage oscilloscope verilog source code has been verified EP2C8Q208C8)

---实现的部分VHDL 程序如下。 　　--- elsif clk1x event and clk1x = 1 then ---if std_logic_vector(length_no) >= “0001” and std_logic_vector(length_no) <= “1001” then -----数据帧数据由接收串行数据端移位入接收移位寄存器---rsr(0) <= rxda --- rsr(7 downto 1) <= rsr(6 downto 0) --- parity <= parity xor rsr(7) --- elsif std_logic_vector(length_no) = “1010” then --- rbr <= rsr --接收移位寄存器数据进入接收缓冲器--- ...... --- end if(--- achieve some VHDL procedure is as follows.--- Elsif clk1x event and then a clk1x = s--- if td_logic_vector (length_no))