基于VHDL的自动售货机实现,包含完整的源代码,锁脚文件以及下载文件

SoC-Wishbone System IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。(SoC-Wishbone System IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.)

在FPGA开发板上用VHDL语言实现了贪吃蛇游戏，开发软件为quartus 2.这是详细的实验报告，包括源码(Snake game with VHDL FPGA development board, software development quartus 2 This is a detailed experimental report, including the source)

全数字fsk调制解调的实现 verilog源码-All-digital realization of fsk modem verilog source code

isa MEMORY PLAN eu biu asm

说明：  Verilog开发的，MII接口的百兆以太网UDP代码(100 megabit Ethernet UDP code of MII interface)

用verilog编写的can总线控制器，包括设计参考历程和仿真程序，以及开发文档！(Written by verilog can bus controller, including the design reference course and simulation program, and the development of the document!)

说明：  fpga串口的发送程序基于verilog语言拿走不用谢。(The sending program of FPGA serial port is based on Verilog language.)

这是一个简单的除法器（32bit/16bit),采用移位相减法-This is a simple divider (32bit/16bit), using phase shift subtraction

6通道正弦波发生器，产生频率，相位，幅值都可调的正弦波形-6-channel sine wave generator, resulting in frequency, phase, amplitude of the sinusoidal waveform are adjustable