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SoC_WishboneSystem
SoC-Wishbone System IP核的VHDL语言源代码,需要的开发环境是QUARTUS II 6.0。(SoC-Wishbone System IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.)
- 2008-01-03 11:14:59下载
- 积分:1
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VHDL_Snake_Game
在FPGA开发板上用VHDL语言实现了贪吃蛇游戏,开发软件为quartus 2.这是详细的实验报告,包括源码(Snake game with VHDL FPGA development board, software development quartus 2 This is a detailed experimental report, including the source)
- 2012-06-25 16:15:26下载
- 积分:1
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全数字fsk调制解调的实现 verilog源码
全数字fsk调制解调的实现 verilog源码-All-digital realization of fsk modem verilog source code
- 2023-04-11 15:55:04下载
- 积分:1
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e_BIU
isa MEMORY PLAN eu biu asm
- 2020-06-25 19:20:02下载
- 积分:1
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ethernet_mii_udp_1
说明: Verilog开发的,MII接口的百兆以太网UDP代码(100 megabit Ethernet UDP code of MII interface)
- 2020-03-20 16:19:21下载
- 积分:1
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can_latest.tar
用verilog编写的can总线控制器,包括设计参考历程和仿真程序,以及开发文档!(Written by verilog can bus controller, including the design reference course and simulation program, and the development of the document!)
- 2015-07-23 19:55:03下载
- 积分:1
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在 2 线液晶电视 DISPLAY(KHỞI TẠO HIỂN THỊ LCD HIỂN THỊ 2 HÀNG) CODE_VHDL_INITIALIZING
- 2022-08-23 23:23:25下载
- 积分:1
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UART_RX_
说明: fpga串口的发送程序基于verilog语言拿走不用谢。(The sending program of FPGA serial port is based on Verilog language.)
- 2020-06-18 04:00:01下载
- 积分:1
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这是一个简单的除法器(32bit/16bit),采用移位相减法
这是一个简单的除法器(32bit/16bit),采用移位相减法-This is a simple divider (32bit/16bit), using phase shift subtraction
- 2022-07-06 17:00:38下载
- 积分:1
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6通道正弦波发生器,产生频率,相位,幅值都可调的正弦波形...
6通道正弦波发生器,产生频率,相位,幅值都可调的正弦波形-6-channel sine wave generator, resulting in frequency, phase, amplitude of the sinusoidal waveform are adjustable
- 2022-10-22 04:00:03下载
- 积分:1