基于VHDL的自动售货机实现,包含完整的源代码,锁脚文件以及下载文件

ATSHA204_S加密芯片资料，学习使用该芯片必读资料(ATSHA204_S encryption chip data, required reading for learning to use the chip)

基于EPM1270的VGA显示器接口源码Verilog-Based on the EPM1270

MAX+plus II编译的模30加法计数器，简单的与非门组成！-MAX+ Plus II compiler module adder 30 counters, a simple composition with the non-door!

利用FPGA实现硬件的VHLD语言的Manchester code。(Hardware implementation using FPGA VHLD language Manchester code.)

vhdl编写的硬件乘法器-prepared by the VHDL hardware multiplier

运用VC编程的带LCD显示的信号发生器可用三个开个调节输出三个波形(Signal generator can be used three to open a regulator output waveform using VC programming with LCD display)

A controller for DDR2 on FPGA with vhdl, content testbench, model and textfile-generation/data-detection using python.

说明：  ask psk 编码调制的vhdl 实现(ask psk coded modulation to achieve the VHDL)

开发板原理图 自己可以设计开发板为什么一定要买呢(Development board schematic can design their own development board why they must buy it)

本文介绍了一个使用 VHDL 描述计数器的设计、综合、仿真的全过程，作为我这一段 时间自学 FPGA/CPLD 的总结，如果有什么不正确的地方，敬请各位不幸看到这篇文章的 大侠们指正，在此表示感谢。当然，这是一个非常简单的时序逻辑电路实例，主要是详细 描述了一些软件的使用方法。文章中涉及的软件有Synplicity 公司出品的Synplify Pro 7.7.1； Altera 公司出品的 Quartus II 4.2；Mentor Graphics 公司出品的 ModelSim SE 6.0。 -This article describes a VHDL description of the use of counter design, synthesis, simulation of the entire process, this time as my self-FPGA/CPLD summary, if what has not the right place, please see this article that, unfortunately, the heroes They correct me, wish to express my gratitude. Of course, this is a very simple example of sequential logic circuit is mainly a detailed description of a number of software usage. Article involved in the software company has produced Synplicity